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intel ? ixp2800 and ixp2850 network processors datasheet product features the intel ? ixp2800 and ixp2850 network processors enable fast deployment of complete content processing by providing unlimited programming flexibility, code re-use, and high-performance pr ocessing. these network processors support a wide variety of wan and lan applications that require support for a broad range of speeds ? currently ranging from oc-3 to oc-192. high-performance and scal ability are achieved through an innovative microengine architecture that include s a multi-threaded distribution cache architecture that enables pipe line features in software. in addition to the standard feature set available with the ixp2800, the ixp2850 integrates functionality for secure networ k traffic at 10 gbits/s. this enables the up-front design of secure network equipment and results in lower overall system cost for power consumption, board real estate, and silicon investment. ? sixteen integrated mi croengines (version 2) ? operating frequency of up to 1.4 ghz ? configurable to four or eight threads per microengine ? 640 dwords of local memory per microengine ? sixteen-entry cam per microengine with single-cycle lookup ? next neighbor bus ac cessing adjacent microengines ? crc unit per microengine ? 8k instructions contro l store per microengine ? support for generalized thread signaling ? integrated intel xscale ? core ? operating frequency of up to 700 mhz ? high performance, low-power 32-bit embedded risc processor ? 32 kbyte instruction cache ? 32 kbyte data cache ? two integrated cryptographic units (ixp2850 only) ? operating frequency of up to 700 mhz ? support for des, 3des , aes, and sha-1 algorithms ? support for aes 128, 192, and 256 bit keys ? three industry standard rdram interfaces ? peak bandwidth of 2.1 gbytes/s ? 800-mhz and 1066-mhz rdram ? error correction code (ecc) ? addressable from intel xscale ? core, microengines, and pci ? four industry standard 32-bit qdr sram interfaces ? peak bandwidth of 1.9 gbytes/s per channel ? up to 233-mhz sram ? hardware support for linked list and ring operations ? atomic bit operations ? atomic arithmetic support ? addressable from intel xscale ? core, microengines, and pci ? integrated media switch fabric interface ? two unidirectional 16-bit low-voltage differential signaling (lvds) data interfaces ? up to 500 mhz per channel ? separately configurable for either spi-4 or csix protocols ? industry standard pci bus ? pci local bus specification, version 2.2* interface for 64-bit 66-mhz i/o ? additional integrated features ? hardware hash unit (48, 64, and 128 bit) ? 16 kbyte scratchpad memory ? serial uart port for debugging ? eight general-purpose i/o pins ? four 32-bit timers ? 1356 ball fcbga package ? dimensions of 37.5 mm x 37.5 mm ? 1 mm solder ball pitch order number: 278537-017
intel ? ixp2800 and ixp2850 network processors 2 datasheet revision history date revision description october 2001 001 release for the customer information book v0.3. december 2001 002 release for the customer information book v0.4. february 2002 003 advanced information version. may 2002 004 release for the ixa sdk 3.0. august 2002 005 updated with miscellaneous changes. october 2002 006 added ixp2850 network processor. december 2002 007 added ixp2850 power va lues and other miscellaneous changes. february 2003 008 removed advance information labeling. april 2003 009 miscellaneous changes. november 2003 010 changed: figures 5 and 27; tables 5, 6, 7, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 41, 42, 43, 45, 47, 51, 56, 60, and 63; sections 3.3, 4.4.8.2, 4.4.9, and 5.1. january 2004 011 added: tables 61, 62; figures 19, 23, and 24. changed: tables 17, 22, 25, 26, 27, 28, 52, and 53; figure 18; section 4.2. april 2004 012 changed: sections 2.6, 3.3, 4.2.2, 4.4.1, 4.4.6, and 5.1; figure 17; tables 8, 22, 23, 24, 26, 28, 30, 32, 33, 39, 40, 42, 43, 51, and 55. july 2004 013 added information for 650 mhz version of ixp2800 and ixp2850 and removed a-stepping information. december 2004 014 miscellaneous updates. june 2005 015 miscellaneous updates. july 2005 016 updated tables 53 and 54 and figures 17 and 18. september 2005 017 updated figures 20 and 21 information in this document is provided in connection wi th intel? products. except as provided in intel?s terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty relating to sale a nd/or use of intel products, including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. intel corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property right s that relate to the presented subject matter. the furn ishing of documents and other materials and info rmation does not provide any license, express or implied, by estoppel or otherwise, to any such patents, tradem arks, copyrights, or other intellectual property rights. intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuc lear facility applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or characteristics of any features or instruct ions marked ?reserved? or ?undefined.? int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the ixp2800 network processors may contain design defects or erro rs known as errata which may cause the product to deviate from published specifications. current characteriz ed errata are available on request. contact your local intel sales office or your distributor to obt ain the latest specifications and before placing your product o rder. copies of documents which have an ordering number and are refer enced in this document, or other intel literature may be obtaine d by calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com . intel and xscale are registered trademarks of intel corporation or its subsidiaries in the united states and other countries. *other names and brands may be claimed as the property of others. copyright ? october 2005, intel corporation
datasheet 3 intel ? ixp2800 and ixp2850 network processors contents 1.0 product description ......................................................................................................... ...7 1.1 hyper task chaining............................................................................................. 7 2.0 functional units............................................................................................................ .... 10 2.1 functional overview............................................................................................ 10 2.2 the intel xscale ? core ....................................................................................... 10 2.3 microengines ....................................................................................................... 11 2.4 cryptography unit ............................................................................................... 11 2.5 rdram ............................................................................................................... 11 2.6 sram .................................................................................................................. 12 2.6.1 qdr clocking scheme .......................................................................... 12 2.6.2 sram controller configurations ............................................................ 13 2.7 media and switch fabric interface ...................................................................... 14 2.7.1 spi-4.2 ................................................................................................... 15 2.7.2 csix ....................................................................................................... 15 2.7.3 flow control bus .................................................................................... 16 2.8 pci controller...................................................................................................... 17 2.9 gpio ................................................................................................................... 17 2.10 serial port............................................................................................................ 18 2.11 slowport .............................................................................................................. 18 3.0 signal description .......................................................................................................... .. 20 3.1 pinout diagram.................................................................................................... 20 3.2 pin description, grouped by function.................................................................21 3.2.1 rdram .................................................................................................. 21 3.2.2 sram ..................................................................................................... 24 3.2.3 media and switch fabric interface (msf) .............................................. 30 3.2.4 pci ......................................................................................................... 34 3.2.5 slowport signals..................................................................................... 37 3.2.6 gpio signals.......................................................................................... 38 3.2.7 serial port signals.................................................................................. 38 3.2.8 clock and reset signals ........................................................................ 38 3.2.9 power supply pins ................................................................................. 39 3.2.10 test and jtag signals .......................................................................... 40 3.2.11 configuration pins .................................................................................. 41 3.2.12 pin state during reset........................................................................... 43 3.2.13 ball assignment...................................................................................... 47 3.2.13.1pins listed in numeric order ....................................................47 3.2.13.2pins listed in alphabetic order ................................................. 67 3.3 pullup/pulldown and unused pin guidelines ...................................................... 87 4.0 electrical specifications................................................................................................... .89 4.1 absolute maximum ratings................................................................................. 89 4.2 supply voltage power-up sequence...... ............................................................. 96 4.2.1 sequence for 1.4 / 1.0 ghz devices ...................................................... 96 4.2.2 sequence for 650 mhz devices............................................................. 96 4.3 lc filter network................................................................................................. 97
intel ? ixp2800 and ixp2850 network processors 4 datasheet 4.4 ac/dc specifications .......................................................................................... 97 4.4.1 clock timing specifications ................................................................... 97 4.4.2 maximum supported operating frequencies....................................... 100 4.4.3 maximum clock frequencies ............................................................... 101 4.4.4 clock dc parameters................... ........................................................ 101 4.4.5 pci i/o unit .......................................................................................... 102 4.4.5.1 pci dc specifications ............................................................. 102 4.4.5.2 pci overshoot/undershoot specifications .............................. 102 4.4.5.3 pci ac specifications ............................................................. 103 4.4.5.4 pci clock signal ac parameter measurements..................... 103 4.4.5.5 pci bus signals timing........................................................... 104 4.4.6 sram ................................................................................................... 105 4.4.7 rdram ................................................................................................ 108 4.4.8 spi-4 and csix .................................................................................... 109 4.4.8.1 dc parameters........................................................................ 109 4.4.8.2 ac parameters........................................................................ 110 4.4.9 flow control bus .................................................................................. 115 4.4.10 slowport i/o buffer ............................................................................... 116 4.4.11 slowport timing ................................................................................... 117 4.4.11.1prom device timing information........................................... 117 4.4.12 gpio .................................................................................................... 119 4.4.13 jtag .................................................................................................... 120 4.4.13.1jtag dc electrical characteristics......................................... 120 4.4.13.2jtag ac characteristics ........................................................ 121 4.4.14 reset timing ........................................................................................ 123 4.4.15 serial port ............................................................................................ 124 5.0 mechanical specifications.............................................................................................. 125 5.1 package marking .............................................................................................. 125 5.2 package dimensions ........................................................................................ 127 figures 1 ixp2800 network processor block diagram......................................................... 8 2 ixp2850 network processor block diagram......................................................... 8 3 ixp2800/ixp2850 network processor based ethernet line card ........................ 9 4 ixp2800/ixp2850 network processor functional block diagram ...................... 10 5 clocking scheme for a qdr interface dr iving four srams .............................. 13 6 spi-4 clock configuration for dual ne twork processors .................................... 15 7 csix flow control interfaces: simplex and full duplex modes ......................... 17 8 generic slowport connection ............................................................................. 19 9 pinout diagram ................................................................................................... 20 10 lc filter network ................................................................................................ 97 11 ref_clk timing ................................................................................................ 98 12 pci clock signal ac parameter measur ements............................................... 103 13 pci bus signals ................................................................................................ 104 14 qdr signal timing ........................................................................................... 107 15 system level reference points ........................................................................ 111 16 reference points for data path timing parameters ......................................... 111 17 spi4-2 receive fifo status bus timing diagram ........................................... 114
datasheet 5 intel ? ixp2800 and ixp2850 network processors 18 spi4-2 transmit fifo status bus timing diagram ..........................................114 19 transient equivalent testing load circu it for slowport i/o buffer ....................117 20 single write transfer fo r self-timing device ....................................................117 21 read transaction for self-timing device ..........................................................118 22 transient equivalent testing load circu it for gpio i/o buffer .........................120 23 vih, vol load for testing ................................................................................121 24 boundary scan general timing ........................................................................121 25 boundary scan three-state timing...................................................................122 26 boundary scan reset timing............................................................................122 27 reset timing .....................................................................................................124 28 ixp2800 network processor package mark ing ................................................126 29 ixp2850 network processor package mark ing ................................................126 30 ixp2800/ixp2850 network processor pack age ball grid array .......................127 31 ixp2800/ixp2850 network processor pa ckage top view ...............................128 32 ixp2800/ixp2850 network processor pa ckage side view ..............................128 tables 1 sram controller configurations ......................................................................... 13 2 qdr address/rpe/wpe mapping...................................................................... 14 3 total memory per channel.................................................................................. 14 4 io signal prefix categories ................................................................................. 21 5 rdram signals .................................................................................................. 21 6 sram signals ..................................................................................................... 24 7 msf data signals ............................................................................................... 30 8 msf flow control signals................................................................................... 33 9 pci signals.......................................................................................................... 35 10 slowport signals.................................................................................................. 37 11 gpio signals....................................................................................................... 38 12 serial port signals............................................................................................... 38 13 clock signals....................................................................................................... 38 14 power supply pins ..............................................................................................39 15 test and jtag signals ....................................................................................... 40 16 configuration pins ............................................................................................... 42 17 pin state during reset........................................................................................ 43 18 ixp2800/ixp2850 network processor fcbg a location pin list........................ 48 19 ixp2800/ixp2850 network pr ocessor alphabetical pin list ............................... 67 20 absolute maximum ratings table.......... ............................................................. 89 21 functional operating temperature rang e.......................................................... 90 22 typical and maximum power .............................................................................. 90 23 functional operating voltage range ? 1.4/1.0 ghz ........................................... 91 24 functional operating voltage range ? 650 mhz................................................ 92 25 example power by supply ? 1.4 ghz .................................................................93 26 example power by supply ? 1.0 ghz .................................................................94 27 example power by supply ? 650 mhz ................................................................ 95 28 ref_clk dc specifications............................................................................... 99 29 ref_clk ac specifications ............................................................................... 99 30 clock rates examples ......................................................................................100 31 maximum supported operating frequencie s....................................................100 32 example maximum clock frequencies .............................................................101
intel ? ixp2800 and ixp2850 network processors 6 datasheet 33 clock buffer dc specifications ......................................................................... 101 34 pci dc specifications ....................................................................................... 102 35 overshoot/undershoot specifications ............................................................... 102 36 maximum loading ............................................................................................. 103 37 66 mhz pci clock signal ac parameters ........................................................ 103 38 33 mhz pci clock signal ac parameters ........................................................ 104 39 33 mhz pci signal timing ................................................................................ 104 40 66 mhz pci signal timing ................................................................................ 105 41 qdr dc specifications ..................................................................................... 105 42 qdr signal timing ........................................................................................... 106 43 qdr clock skew .............................................................................................. 106 44 rdram dc parameters ................................................................................... 108 45 rdram loading ............................................................................................... 108 46 rdram ac parameters ................................................................................... 109 47 spi-4 lvttl dc thresholds ............................................................................ 110 48 spi-4 lvds driver dc specifications .... ........................................................... 110 49 spi-4 lvds receiver dc specifications .......................................................... 110 50 data path interface timing (static alignment) .................................................. 112 51 data path interface timing (dynamic a lignment) ............................................. 112 52 transmitter and receiver ac timing pa rasitics .............................................. 113 53 spi4-2 receive fifo status bus timing parameters ...................................... 114 54 spi4-2 transmit fifo status bus timing parameters ..................................... 115 55 flow control bus lvds driver dc specifications ............................................ 115 56 flow control bus lvds receiver dc specifications ........................................ 115 57 flow control bus clock specifications.............................................................. 116 58 slowport i/o buffer dc specifications .............................................................. 116 59 slowport write ac parameters ........................................................................ 118 60 slowport read ac parameters ......................................................................... 119 61 gpio i/o buffer dc specifications ................................................................... 119 62 jtag dc specifications.................................................................................... 120 63 jtag ac specifications .................................................................................... 123 64 reset timing specification................................................................................ 123 65 ixp2800/ixp2850 network processor package dimensions ........................... 129
intel ? ixp2800 and ixp2850 network processors product description datasheet 7 1.0 product description the intel ? ixp2800 and ixp2850 network processors are second-generat ion high-performance network processors based on the first generation intel ? ixp1200 network processor design. they are fully programmable network processors that implement a high-perform ance parallel processing architecture on a single chip designed for processi ng complex algorithms, d eep packet inspection, traffic management, and forwarding at wire-speed . its store-and-forward architecture combines a high-performan ce intel xscale ? core with sixteen 32-bit independent multithreaded microengines that cumulatively provide more than 25 giga-opera tions per second. the microengines provide the processing power to perform dataplane tasks th at traditionally required expensive high-speed asics. intel?s second-generation network processors are the first implementation of intel?s hyper task chaining technology. this unique network processing approach allows a si ngle stream packet/cell processing problem to be decomposed into multipl e, sequential tasks that can be linked together easily. the hardware design uses fast and flexible sharing of data and ev ent signals among threads and microengines to manage data-dependent opera tions using multiple parallel processing stages, with low latency. through this combination of flexible software pipelining and fast inter-process communication, hyper task chaining delivers rich processing capability at oc-192/10 gbps line rates. 1.1 hyper task chaining hyper task chaining implements several significant innovations to ensure low latency communication among processes. these mechanisms include ?n ext neighbor? registers that enable individual microengines to rapidly pass data and st ate information to adjacent microengines. reflector mode pathways ensure that data and global event signals can be shared with multiple microengines, using 32-bit unidirectio nal buses that connect the network processor?s internal processing and memory resources. a thir d enhancement, ring buffer registers, provides a highly efficient mechanism for flexibly linking tasks among multiple software pipelines. ring buffers allow developers to establish ?producer-consumer? relationships among microengines, efficiently propagating results along the pipeline in fifo order. to minimize latency associated with external memory referen ces, register structures are complemented by 16 entries of content addressable memory (cam) asso ciated with each microe ngine. configured as a distributed cache, the ca m enables multiple threads and micr oengines to manipulate the same data simultaneously, while ma intaining data coherency. figure 1 is a block diagram of the ixp2800 network processor, and figure 2 is a block diagram of the ixp2850 network processor. figure 3 shows two ixp2800 network processors in a typical 10 gb/s full duplex line card with a switch fabric interface.
intel ? ixp2800 and ixp2850 network processors product description 8 datasheet figure 1. ixp2800 network processor block diagram figure 2. ixp2850 network processor block diagram intel xscale? core 32k ic 32k dc mev2 10 mev2 11 mev2 12 mev2 15 mev2 14 mev2 13 rbuf 64 @ 128b tbuf 64 @ 128b hash 64/48/128 scratch 16kb qdr sram 2 qdr sram 1 rdram 1 rdram 3 rdram 2 g a s k e t pci (64b) 66 mhz ixp2800 ixp2800 16b 16b 16b 16b 18 18 18 18 18 18 18 18 18 18 18 18 18 18 64b 64b s p i 4 or c s i x stripe e/d q e/d q qdr sram 3 e/d q 18 18 18 18 mev2 9 mev2 16 mev2 2 mev2 3 mev2 4 mev2 7 mev2 6 mev2 5 mev2 1 mev2 8 csrs -fast_wr -uart -timers -gpio -bootrom/slowport qdr sram 4 e/d q 18 18 18 18 intel xscale? core 32k ic 32k dc mev2 10 mev2 11 mev2 12 mev2 15 mev2 14 mev2 13 rbuf 64 @ 128b tbuf 64 @ 128b hash 64/48/128 scratch rings 16kb qdr sram 2 qdr sram 1 rdr 1 rdr 3 rdr 2 g a s k e t pci (64b) 66 mhz ixp2850 network processor ixp2850 network processor 16b 16b 16b 16b 18 18 18 18 18 18 18 18 18 18 18 18 18 18 64b 64b s p i 4 or c s i x stripe/byte align e/d q e/d q qdr sram 3 e/d q 18 18 18 18 mev2 9 mev2 16 mev2 2 mev2 3 mev2 4 mev2 7 mev2 6 mev2 5 mev2 1 mev2 8 csrs -fast_wr -uart -timers -gpio -bootrom/slowport qdr sram 4 e/d q 18 18 18 18 crypto crypto 1 1 crypto crypto 2 2
intel ? ixp2800 and ixp2850 network processors product description datasheet 9 figure 3. ixp2800/ixp2850 network processor based ethernet line card 10gbe spi i/f fabric csix i/f rdr packet memory ixf18101 10gbs 15gbs 15gbs 10gbs pci 64/66 sar?ing classification metering policing initial congestion management ingress processor traffic shaping flexible choices diff serve tm 4.1 ? egress processor ixp2800/ixp2850 egress processor d d r r a a m m d d r r a a m m d d r r a a m m q q d d r r q q d d r r q q d d r r qdr sram queues & tables q q d d r r ixp2800/ixp2850 ingress processor d d r r a a m m d d r r a a m m d d r r a a m m q q d d r r q q d d r r q q d d r r rdr packet memory qdr sram queues & tables q q d d r r 10 gbe wan/lan cdr, demux control plane processor flow ctl fabric interface chip (fic)
intel ? ixp2800 and ixp2850 network processors functional units 10 datasheet 2.0 functional units 2.1 functional overview this section provides a brief overview of the ixp2800 and ixp2850 network processor internal hardware. figure 4 shows the major internal blocks. 2.2 the intel xscale ? core the intel xscale ? core is a 32-bit general-purpose risc pro cessor. it incorporat es an extensive list of architectural features that enab le it to achieve high performance. it is compatible to the arm* version 5 (v5) architecture. it implements the integer instruction set of arm v5, but does not provide hardware support for the floating-point instructions. the intel xscale ? core provides the thumb instruction set (arm v5t) and the arm v5e dsp extensions. backward compatibility with the first generation of strongarm* products is maintained for user-mode applications. operat ing systems may require modifications to match the specific hardware features of the intel xscale ? core and to take advantage of the performance enhancements added to it. figure 4. ixp2800/ixp2850 network processor functional block diagram b0564-02 media switch fabric (msf) scratched memory sram controller 0 sram controller 1 sram controller 2 sram controller 3 dram controller 0 dram controller 1 dram controller 2 hash unit crypto 0 crypto 1 intel? ixp2850 network processor only pci controller cap me cluster 0 me 0x1 me 0x0 me 0x2 me 0x3 me 0x5 me 0x4 me 0x6 me 0x7 me cluster 1 me 0x10 me 0x11 me 0x13 me 0x12 me 0x14 me 0x15 me 0x17 me 0x16 intel xscale ? core peripherals (xpi) intel xscale ? core performance monitor
intel ? ixp2800 and ixp2850 network processors functional units datasheet 11 2.3 microengines the microengines do most of the programmable pe r-packet processing in the network processor. there are 16 microengines, connected as shown in figure 4 . the microengines can access all of the shared resources (sram, dram, msf, etc. ) and the private connect ions between adjacent microengines. the microengines provide support for software-controlled multi-threaded operation. given the disparity in processor cycle times compared to external memory time s, a single thread of execution often blocks, waiting for external memory oper ations to complete. multiple threads enable interleave operations ? there is usually at least one thread ready to run while others are waiting. 2.4 cryptography unit the ixp2850 network processor has two cr yptography units ? crypto 0 and crypto 1 (see figure 4 ) that perform bulk data encryption an d authentication. the cryptography units interface only to the microengines and media switc h fabric, and contain input ram available for receiving input data from th e microengine and rbuf (receive buffer) elements. both cryptography units support the data encryptio n standard (des), triple des (3des), and advanced encryption standard (aes) algorithms, and secure hash algorithm (sha-1) hashing. each cryptography unit has two 3des cores, one aes core, and two sha-1 cores: ? each 3des core can access thr ee encryption/decryption key stat es and three initialization vectors (iv). ? the aes core can access six key states and six ivs. ? the 3des and aes cores can be used with or without cipher block chaining. ? the aes cores support a block size of 128 bits, and key lengths of 128, 192, and 256 bits. ? the sha-1 cores have hardware support to implement the keyed-hash message authentication code (hmac) algorithm, with minimal microengine intervention. ? the cryptography units operate at half the microengine frequency. 2.5 rdram the ixp2800/ixp2850 has controllers for three rambus* dram (rdram) channels. each of the controllers independently accesses its own rdrams, and can operate concurre ntly with the other controllers (i.e., they are not op erating as a single, wider memory). dram provides high density, high bandwidth storage and is typically used for data buffers. rdram sizes of 64, 128, 256, and 512 mbytes, a nd 1 gbyte are supported. however, each of the channels must have the same number, size, and speed of rdrams populated. each channel can be populated with one to four per bank, for s hort-channel and one rimm for long-channel. up to two gbytes of dram is supported. if less th an two gbytes of memory is available, the upper part of the address space is not used. it is also possible (for system cost and area savings) to have channels 0 and 1 populated with channel 2 empty, or channel 0 populated with channels 1 and 2 empty.
intel ? ixp2800 and ixp2850 network processors functional units 12 datasheet reads and writes to rdram are generated by microengines, intel xscale ? core, and pci (external bus masters and dma channels). the c ontrollers also do refres h and calibration cycles to the rdrams, transparently to software. note: rdram powerdown and nap modes are not supported. hardware interleaving of addresses (also called striping) provides balanced access to all populated channels; the interleave size is 128 bytes. interleaving helps to maintain utilization of available bandwidth by spreading consecutive accesses to mu ltiple channels. the interleaving is done in the hardware so that the three channels appear to software as a single contiguous memory space. ecc (error correcting code) is s upported, but can be disabled. enabling ecc requires that x18 rdrams be used; if ecc is disa bled, x16 rdrams can be used. e cc can detect and correct all single-bit errors, and detect all double-bit errors. when ecc is enabled, partial writes (writes of less than eight bytes) must be done as read-modify-writes. 2.6 sram the network processor has four independent sram controllers, each of which supports pipelined qdr synchronous static ram (sram) and/or a coprocessor that adheres to qdr signaling. any or all controllers can be left unpopulated if the application does not need to use them. sram is accessible by the microengines, the intel xscale ? core, and the pci unit (external bus masters and dma). the memory is logically four bytes (32-bits) wide; physically, the data pins are two bytes wide and are double-clocked. byte parity is supported, and each of the four bytes has a parity bit, which is written when the byte is written and checked when the data is read. there are byte enables that select the bytes to be written, for writes of less than 32-bits. each of the four qdr ports are qdr- and qdrii-c ompatible; each port im plements the ?_k? and ?_c? output clocks and ?_cin? as an input and their inversions. ( note : the ?_c? and ?_cin? clocks are optional). extensive work has been done to provide impedan ce controls within the ixp2800/ixp2850 for ixp2800/ixp2850-initiated signals driving to qdr parts. providing a clean signaling environment is critical to achievi ng 200- to 233-mhz qdrii data transfers. the configuration assumptions for the network pr ocessor i/o driver/receive r development includes four qdr loads and the network pr ocessor. the network processor supports bursts of two srams (bursts of four srams are not supported). the sram controller can also be co nfigured to interface to an extern al coprocessor that adheres to the qdr electricals and protocol. each sram c ontroller can also inte rface to an external coprocessor through its standard qdr interface. this interface enables both sram devices and coprocessors to operate on the same bus. the coprocessor behaves as a memory-mapped device on the sram bus. 2.6.1 qdr clocking scheme the controller drives out two pairs of k clock (k and k#), and two pairs of c clock (c and c#). both c/c# clocks externally return to the controller for reading data. figure 5 shows the clock diagram of the clocking scheme for a qdr interface driving four sram chips.
intel ? ixp2800 and ixp2850 network processors functional units datasheet 13 2.6.2 sram controll er configurations each channel has enough address pins (24) to support up to 64 mbyte of sram. the sram controllers can directly generate multiple port enables (up to four pairs) to allow for depth expansion. two pairs of pins are dedicated fo r port enables. smaller rams use fewer address signals than the number provided to accommodate the largest ra ms, so some address pins (23:20) are configurable as either address or port-e nable, based on the csr setting as shown in table 1 . note: all of the srams on a given ch annel must be the same size. figure 5. clocking scheme for a qdr interface driving four srams a9234-03 clam-shelled srams package balls package balls termination intel? ixp2800 network processor c0in/c0in# k0/k0# k/k# k/k# c/c# c/c# c0/c0# k1/k1# c1/c1# c0/c0# c1/c1# c1in/c1in# termination table 1. sram controller configurations sram configuration sram size addresses needed to index sram addresses used as port enables total number of port select pairs available 512k x 18 1 mbyte 17:0 23:22, 21:20 4 1m x 18 2 mbyte 18:0 23:22, 21:20 4 2m x 18 4 mbyte 19:0 23:22, 21:20 4 4m x 18 8 mbyte 20:0 23:22 3 8m x 18 16 mbyte 21:0 23:22 3 16m x 18 32 mbyte 22:0 none 2 32m x 18 64 mbyte 23:0 none 1
intel ? ixp2800 and ixp2850 network processors functional units 14 datasheet each channel can be expanded by depth, accordin g to the number of port enables available. if external decoding is used, then the number of srams used is not limited by the number of port enables generated by the sram controller. note: external decoding may require external pipe line registers to account for the decode time, depending on the desired frequency. table 2 lists the qdr address/rpe/wpe mapping. maximum sram system sizes are shown in table 3 . shaded entries require external decoding, because they use more port enables than the sram controller can supply directly. 2.7 media and switch fabric interface the media and switch fabric (msf) interface conn ects the network processor to a physical layer device (phy) and/or a switch fa bric interface. the msf consists of the following external interfaces: ? receive and transmit interfaces, each of which can be individually config ured for either the spi-4 phase 2 (system packet interface) to a ph y or the csix?l1 protoc ol to a switch fabric. ? a flow control interface, which provides a point-t o-point connection used primarily to pass csix-l1 flow control c-frames either between two network processors or between a network processor and a switch fabric. table 2. qdr address/rpe/wpe mapping sram configuration/size sram_control [sram_size][9:7] sram_control [port_ctl][5:4] rpe[2]/wpe[2] rpe[3]/wpe[3] 512k x 18 - 1mb 000 11 qdr_addr[23:22] qdr_addr[21:20] 1mb x 18 - 2mb 001 11 qdr_addr[23:22] qdr_addr[21:20] 2mb x 18 - 4mb 010 11 qdr_addr[23:22] qdr_addr[21:20] 4mb x 18 - 8mb 011 10 qdr_addr[23:22] n/a 8mb x 18 - 16mb 100 10 qdr_addr[23:22] n/a 16mb x 18 - 32mb 101 00 n/a n/a 32mb x 18 - 64mb 110 00 n/a n/a table 3. total memory per channel sram size number of srams on channel 12345678 512k x 18 1 mb 2 mb 3 mb 4 mb 5 mb 6 mb 7 mb 8 mb 1m x 18 2 mb 4 mb 6 mb 8 mb 10 mb 12 mb 14 mb 16 mb 2m x 18 4 mb 8 mb 12 mb 16 mb 20 mb 24 mb 28 mb 32 mb 4m x 18 8 mb 16 mb 24 mb 32 mb 64 mb na na na 8m x 18 16 mb 32 mb 48 mb 64 mb na na na na 16m x 18 32 mb 64 mb na na na na na na 32m x 18 64 mb na na na na na na na
intel ? ixp2800 and ixp2850 network processors functional units datasheet 15 the msf supports 16-bit ddr lvds signaling for the spi-4 data path channel, and can be configured to support either lvttl or lvds si gnaling for the spi-4 fifo status channel. the msf supports 16-bit lvds signaling for csix-l1 pr otocol and 4-bit lvds signaling for the flow control interface. 2.7.1 spi-4.2 spi-4.2 is an interface for packet and cell transfer between a physical layer (phy) device and a link layer device (network processor) , for aggregate bandwidths of oc-192 atm and packet over sonet/sdh (pos), as well as 10 gb/s ethernet applications. the spi-4.2 protocol tran sfers data in bursts of variable le ngth. associated with each burst is information such as port number (for a multi-port device such as a 10 x 1 gbe), sop, and eop. this information is collected by the msf and passed to the microengines. there are two options that do not require an extra oscillator to provide a clock for the data that moves between two network processors on the same line card: ? in the first option, the mac device creates an rd_clk to the first network processor, as shown in figure 6 . rclk_ref loops back into tclk_ref for network processor 1, and tclk_ref is used as the source of the td_clk to network processor 2. ? in the second option, the td_clk from networ k processor 1 to network processor 2 can be created using a divide of network processor 1?s in ternal fast clock. the multiplex that selects between the two possible sources of td_clk is controlled by a bit in the msf_tx_control csr. the optical internetworking forum (oif) cont rols the spi-4.2 impl ementation agreement document (available at http://www.oiforum.com). 2.7.2 csix csix-l1 (common switch interface, level 1) de fines an interface between a traffic manager (tm) and a switch fabric (sf) for atm, ip, mp ls, ethernet, and similar data communication applications. the network processor forum (npf) controls the csix-l1 specifi cation (available at http://www.npforum.org and www.csix.org). figure 6. spi-4 clock configurat ion for dual network processors a9317-01 ixp2800 #1 mac rd clk rclk ref tclk ref td clk ixp2800 #2 rd clk rclk ref tclk ref td clk
intel ? ixp2800 and ixp2850 network processors functional units 16 datasheet the unit of information transferred between traf fic managers and switch fabrics is called a cframe. there are three categories of cframes: ? data ? control (one type of which is flow control) ? idle the msf automatically discards any idle cframes th at it receives from the sf, and transmits idle cframes to the sf when required. the msf stor es data and control cframes in buffers during transmit and receive operations. the buffers may be partitioned according to cframe category ? guaranteeing that neithe r control nor data cframes will block each other. there are two types of csix-l1 flow control: ? link level ? virtual output queue (voq) every cframe base header contains a ready fiel d, which contains two link level flow control bits: one for flow control traffic and one for data traffic. due to the csix-l1 requirement for bounded response to link level flow control, the msf manages all link level flow control. virtual output queue flow control is carried in flow control cframes. as with data cframes, the msf places flow control cframes in internal bu ffers before passing them to the microengines for processing. 2.7.3 flow control bus the msf flow control bus passes csix-l1 flow control cframes between two network processors or between a switch fabric and a single network processor. the bus is implemented as two independent unidirectional buses. it uses lvds signaling with the same clocking rate as the msf receive and transmit channels, and has a 4-bi t data bus ? yielding an available bandwidth equal to 25 percent of the receive and transmit channels. the flow control bus can be configured in one of two modes: ? dual chip, full duplex mo de for applications where the fabr ic interface uses the transmit and receive channels to pass flow control cframes ? simplex mode for applications wh ere the fabric interface is desi gned to use the flow control bus to pass flow control cframes when the ixp2800/ixp2850 is configured in dual chip, full duplex mode, the egress ixp2800/ixp2850 automatically forwards cframe s received from the switch fabric across the flow control bus to the ingress ixp2800/ixp2 850. additionally, the egress ixp2800/ixp2850 sends incoming and outgoing link level flow control information across the flow control serial bus to the ingress ixp2800/ixp2850. when the ixp2800/ixp2850 is configured in si mplex mode, the flow c ontrol bus signals are connected directly to the switch fabric. the egress ixp2800/ixp2850 sends flow control cframes directly to the switch fabric, and the sw itch fabric sends flow control cframes directly to the ingress ixp2800/ixp2850. figure 7 shows the ixp2800 conn ected in both modes.
intel ? ixp2800 and ixp2850 network processors functional units datasheet 17 2.8 pci controller the pci controller provides a 64-bit, 66 mhz-capable pci local bus specification, version 2.2* interface. it is also compatible to 32-bit and/or 33 mhz pci devi ces. the pci controller provides the following functions: ? target access (external bus master access to sram, dram, and csrs) ? master access (intel xscale ? core or microengine acces s to pci target devices) ? two dma channels ? mailbox and doorbell registers for intel xscale ? core to host communication ? pci arbiter the network processor can be conf igured to act as a pci central function (for use in a stand-alone system), where it provides the pci reset signal, or as an add-in device, where it uses the pci reset signal as the chip reset input. 2.9 gpio the network processor contains eight general purp ose i/o (gpio) pins. th ese can be programmed as either input or output, and can be used for slow speed i/o, such as leds or input switches. they can also be used as interrupts to the intel xscale ? core, or to clock the programmable timers. figure 7. csix flow control interfaces: simplex and full duplex modes a9391-02 csix r x serial bus flow control bus csix tx ingress intel ixp2800 network processor egress intel ixp2800 network processor switch fabric interface fcififo msf csix r x csix flow control interface: simplex mode csix flow control interface: full duplex mode flow control tx ingress intel ? ixp2800 network processor egress intel ixp2800 network processor switch fabric interface fcififo fcefifo csix tx flow control r x
intel ? ixp2800 and ixp2850 network processors functional units 18 datasheet 2.10 serial port the network processor contains a standard rs-232 compatible universal asynchronous receiver/transmitter (uart), which can be us ed for communication with a debugger or maintenance console. modem controls are not supported; if they are needed, gpio pins can be used for that purpose. the uart performs serial-to-parallel conversion on data characters recei ved from a peripheral device and parallel-to-serial conversion on data characters received from the processor. the processor can read the complete status of the uar t at any time during operat ion. available status information includes the type an d condition of the transfer oper ations being performed by the uart and any error conditions (parity, overrun, framin g, or break interrupt). the serial ports can operate in either fifo or non-fifo mode. in fifo mode, a 64-byte transmit fifo holds data from th e processor to be transmitted on the se rial link and a 64-byte receive fifo buffers data from the serial link, until the data is read by the processor. the uart includes a programmable baud rate generator, which is capable of dividing the internal clock input by divisors of 1 to 2 16 - 1 and produces a 16x clock that drives the internal transmitter logic and the receive logic. the ua rt can be operated in polled or in interrupt-driven mode, as selected by software. 2.11 slowport the slowport is an external interface to the netw ork processor, and is used for 8-bit flash rom access and 8, 16, or 32-bit mi croprocessor device access. it allows the intel xscale ? core to do read/write data transfers to these slave devices. the slowport supports 4-, 8-, and 16-mbyte flash sizes. the address bus and data bus are multiplexed to redu ce the pincount. in addition, 24 bits of address are shifted out on three clock cycles . therefore, an external set of buffers is needed to latch the address; two chip sel ects are provided ? see figure 8 (note that the ack signal is optional).
intel ? ixp2800 and ixp2850 network processors functional units datasheet 19 figure 8. generic slowport connection a9318-02 sp_rd_l sp_cs_l[0] sp_cs_l[1] sp_a[1:0] ce# cp d[7:0] q[7:0] 74f377 sp_wr_l oe_l a[1:0] cs_l we_l d[7:0] a[24:2] a[1:0] cs_l we_l d[7:0] ack_l a[24:2] intel ? ixp2800 network processor sp_ad[7:0] sp_ale_l sp_clk sp_ack_l ce# cp d[7:0] a[24:18] a[17:10] a[9:2] q[7:0] 74f377 ce# cp d[7:0] q[7:0] 74f377 oe_l
intel ? ixp2800 and ixp2850 network processors signal description 20 datasheet 3.0 signal description 3.1 pinout diagram figure 9. pinout diagram a9625-01 1 2 3 4 5 6 7 8 9 1011121314 au at ar ap an am al ak aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 1011121314 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 bottom (pin side) view 31 32 33 34 35 36 37 au at ar ap an am al ak aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 31 32 33 34 35 36 37 pci vcc/vss qdr3 qdr1 sp14 qdr2 qdr0 slow port rdr0 rdr1 rdr2
intel ? ixp2800 and ixp2850 network processors signal description datasheet 21 3.2 pin description, grouped by function this section provides an overview of the networ k processor i/o signals. detailed definitions and descriptions of signal usage can be found in sections specific to each interface. the network processor signals are categorized into one of several groups, as shown in table 4 . 3.2.1 rdram there are three channels of rd ram. the i/o design supports long-channel and short-channel board implementations. long-channel is rimm based, and short-channel is board-mounted. the rdr channels support pc600, pc800, and 1066-mhz rdr parts. the rdr channels allow programmatic selection of ecc. long- and sh ort-channel design guides are available from rambus*. the long-channel design supports one rimm load. there are three rambus* dram (rdram) channels , and each channel has the signals shown in table 5 . the drams use rsl signaling levels, with the exception of sio, cmd, sck, pclkm, and synclkn, which are cmos. table 4. io signal prefix categories io signal group prefix description clk clocks, reset, and test control signals related to the pll clock sp slowport test test port jtag joint test action group gpio general purpose io sr serial port spi4 spi-4 fc flow control qdrn four qdr ports rdrn three rambus* ports pci pci table 5. rdram signals (sheet 1 of 3) signal name i/o description number rdr0_sio rdr1_sio rdr2_sio i/o serial data 3 rdr0_cmd rdr1_cmd rdr2_cmd o command 3 rdr0_sck rdr1_sck rdr2_sck o serial clock 3
intel ? ixp2800 and ixp2850 network processors signal description 22 datasheet rdr0_dqa(0) rdr0_dqa(1) rdr0_dqa(2) rdr0_dqa(3) rdr0_dqa(4) rdr0_dqa(5) rdr0_dqa(6) rdr0_dqa(7) rdr0_dqa(8) rdr1_dqa(0) rdr1_dqa(1) rdr1_dqa(2) rdr1_dqa(3) rdr1_dqa(4) rdr1_dqa(5) rdr1_dqa(6) rdr1_dqa(7) rdr1_dqa(8) rdr2_dqa(0) rdr2_dqa(1) rdr2_dqa(2) rdr2_dqa(3) rdr2_dqa(4) rdr2_dqa(5) rdr2_dqa(6) rdr2_dqa(7) rdr2_dqa(8) i/o low byte 27 rdr0_dqb(0) rdr0_dqb(1) rdr0_dqb(2) rdr0_dqb(3) rdr0_dqb(4) rdr0_dqb(5) rdr0_dqb(6) rdr0_dqb(7) rdr0_dqb(8) rdr1_dqb(0) rdr1_dqb(1) rdr1_dqb(2) rdr1_dqb(3) rdr1_dqb(4) rdr1_dqb(5) rdr1_dqb(6) rdr1_dqb(7) rdr1_dqb(8) rdr2_dqb(0) rdr2_dqb(1) rdr2_dqb(2) rdr2_dqb(3) rdr2_dqb(4) rdr2_dqb(5) rdr2_dqb(6) rdr2_dqb(7) rdr2_dqb(8) i/o high byte 27 par0_padvrefa par0_padvrefb par1_padvrefa par1_padvrefb par2_padvrefa par2_padvrefb i logic threshold voltage for rsl 6 table 5. rdram signals (sheet 2 of 3) signal name i/o description number
intel ? ixp2800 and ixp2850 network processors signal description datasheet 23 rdr0_cfm rdr1_cfm rdr2_cfm o clock from master (high) 3 rdr0_cfmn rdr1_cfmn rdr2_cfmn o clock from master (low) 3 rdr0_ctm rdr1_ctm rdr2_ctm i clock to master (high) 3 rdr0_ctmn rdr1_ctmn rdr2_ctmn i clock to master (low) 3 rdr0_rq(5) rdr0_rq(6) rdr0_rq(7) rdr1_rq(5) rdr1_rq(6) rdr1_rq(7) rdr2_rq(5) rdr2_rq(6) rdr2_rq(7) o row[2:0] 9 rdr0_rq(0) rdr0_rq(1) rdr0_rq(2) rdr0_rq(3) rdr0_rq(4) rdr1_rq(0) rdr1_rq(1) rdr1_rq(2) rdr1_rq(3) rdr1_rq(4) rdr2_rq(0) rdr2_rq(1) rdr2_rq(2) rdr2_rq(3) rdr2_rq(4) o column[4:0] 15 rdr0_pclkm rdr1_pclkm rdr2_pclkm o phase detector output to drcg = internal rdram clk/4 3 rdr0_sclkn rdr1_sclkn rdr2_sclkn o phase detector output to drcg = ctm/16 3 to ta l 111 table 5. rdram signals (sheet 3 of 3) signal name i/o description number
intel ? ixp2800 and ixp2850 network processors signal description 24 datasheet 3.2.2 sram there are four sram interfaces to quad data rate (qdr) srams, and each interface has the signals found in table 6 . the srams use hstl signaling levels. table 6. sram signals (sheet 1 of 7) signal name i/o description number qdr0_k_h(0) qdr0_k_h(1) qdr1_k_h(0) qdr1_k_h(1) qdr2_k_h(0) qdr2_k_h(1) qdr3_k_h(0) qdr3_k_h(1) o positive and negative output clocks . address, port enable, data out are referenced to these clocks. 8 qdr0_k_l(0) qdr0_k_l(1) qdr1_k_l(0) qdr1_k_l(1) qdr2_k_l(0) qdr2_k_l(1) qdr3_k_l(0) qdr3_k_l(1) o 8 qdr0_c_h(0) qdr0_c_h(1) qdr1_c_h(0) qdr1_c_h(1) qdr2_c_h(0) qdr2_c_h(1) qdr3_c_h(0) qdr3_c_h(1) o positive input clocks. data in is referenced to these clocks. 8 qdr0_c_l(0) qdr0_c_l(1) qdr1_c_l(0) qdr1_c_l(1) qdr2_c_l(0) qdr2_c_l(1) qdr3_c_l(0) qdr3_c_l(1) o negative input clocks. data in is referenced to these clocks. 8 qdr0_cin_h(0) qdr0_cin_h(1) qdr1_cin_h(0) qdr1_cin_h(1) qdr2_cin_h(0) qdr2_cin_h(1) qdr3_cin_h(0) qdr3_cin_h(1) i positive clock inputs. these di fferential clocks are used as a reference for data in. they are the feedback of sn_c and sn_c_l. note : qdrn_cin_l(1) and qdrn_cin_h(1) input pad outputs are not connected/used internally. the qdrn_cin_l(1) and qdrn_cin_h(1) input pins/pads are provided in the device and can be used for termination. 8 qdr0_cin_l(0) qdr0_cin_l(1) qdr1_cin_l(0) qdr1_cin_l(1) qdr2_cin_l(0) qdr2_cin_l(1) qdr3_cin_l(0) qdr3_cin_l(1) i 8
intel ? ixp2800 and ixp2850 network processors signal description datasheet 25 qdr0_q_h(0) qdr0_q_h(1) qdr0_q_h(2) qdr0_q_h(3) qdr0_q_h(4) qdr0_q_h(5) qdr0_q_h(6) qdr0_q_h(7) qdr0_q_h(9) qdr0_q_h(10) qdr0_q_h(11) qdr0_q_h(12) qdr0_q_h(13) qdr0_q_h(14) qdr0_q_h(15) qdr0_q_h(16) i data input bus. 16 qdr0_q_h(8) qdr0_q_h(17) i byte parity for data in qdr0_q_h(17) and qdr0_q_h(8) correspond to qdr0_q_h[16:9] and qdr0_q_h[7:0] respectively. 2 qdr0_d_h(0) qdr0_d_h(1) qdr0_d_h(2) qdr0_d_h(3) qdr0_d_h(4) qdr0_d_h(5) qdr0_d_h(6) qdr0_d_h(7) qdr0_d_h(9) qdr0_d_h(10) qdr0_d_h(11) qdr0_d_h(12) qdr0_d_h(13) qdr0_d_h(14) qdr0_d_h(15) qdr0_d_h(16) o data output bus. 16 qdr0_d_h(8) qdr0_d_h(17) o byte parity for data in qdr0_d_h(17)] and qdr0_d_h(8) correspond to qdr0_d_h[16:9] and qdr0_d_h[7:0] respectively. 2 qdr1_q_h(0) qdr1_q_h(1) qdr1_q_h(2) qdr1_q_h(3) qdr1_q_h(4) qdr1_q_h(5) qdr1_q_h(6) qdr1_q_h(7) qdr1_q_h(9) qdr1_q_h(10) qdr1_q_h(11) qdr1_q_h(12) qdr1_q_h(13) qdr1_q_h(14) qdr1_q_h(15) qdr1_q_h(16) i data input bus. 16 qdr1_q_h(8) qdr1_q_h(17) i byte parity for data in qdr1_q_h(17) and qdr1_q_h(8) correspond to qdr1_q_h[16:9] and qdr1_q_h[7:0] respectively. 2 table 6. sram signals (sheet 2 of 7) signal name i/o description number
intel ? ixp2800 and ixp2850 network processors signal description 26 datasheet qdr1_d_h(0) qdr1_d_h(1) qdr1_d_h(2) qdr1_d_h(3) qdr1_d_h(4) qdr1_d_h(5) qdr1_d_h(6) qdr1_d_h(7) qdr1_d_h(9) qdr1_d_h(10) qdr1_d_h(11) qdr1_d_h(12) qdr1_d_h(13) qdr1_d_h(14) qdr1_d_h(15) qdr1_d_h(16) o data output bus. 16 qdr1_d_h(8) qdr1_d_h(17) o byte parity for data in qdr1_d_h(17)] and qdr1_d_h(8) correspond to qdr1_d_h[16:9] and qdr1_d_h[7:0] respectively. 2 qdr2_q_h(0) qdr2_q_h(1) qdr2_q_h(2) qdr2_q_h(3) qdr2_q_h(4) qdr2_q_h(5) qdr2_q_h(6) qdr2_q_h(7) qdr2_q_h(9) qdr2_q_h(10) qdr2_q_h(11) qdr2_q_h(12) qdr2_q_h(13) qdr2_q_h(14) qdr2_q_h(15) qdr2_q_h(16) i data input bus. 16 qdr2_q_h(8) qdr2_q_h(17) i byte parity for data in qdr2_q_h(17) and qdr2_q_h(8) correspond to qdr2_q_h[16:9] and qdr2_q_h[7:0] respectively. 2 qdr2_d_h(0) qdr2_d_h(1) qdr2_d_h(2) qdr2_d_h(3) qdr2_d_h(4) qdr2_d_h(5) qdr2_d_h(6) qdr2_d_h(7) qdr2_d_h(9) qdr2_d_h(10) qdr2_d_h(11) qdr2_d_h(12) qdr2_d_h(13) qdr2_d_h(14) qdr2_d_h(15) qdr2_d_h(16) o data output bus. 16 qdr2_d_h(8) qdr2_d_h(17) o byte parity for data in qdr2_d_h(17)] and qdr2_d_h(8) correspond to qdr2_d_h[16:9] and qdr2_d_h[7:0] respectively. 2 table 6. sram signals (sheet 3 of 7) signal name i/o description number
intel ? ixp2800 and ixp2850 network processors signal description datasheet 27 qdr3_q_h(0) qdr3_q_h(1) qdr3_q_h(2) qdr3_q_h(3) qdr3_q_h(4) qdr3_q_h(5) qdr3_q_h(6) qdr3_q_h(7) qdr3_q_h(9) qdr3_q_h(10) qdr3_q_h(11) qdr3_q_h(12) qdr3_q_h(13) qdr3_q_h(14) qdr3_q_h(15) qdr3_q_h(16) i data input bus. 16 qdr3_q_h(8) qdr3_q_h(17) i byte parity for data in qdr3_q_h(17) and qdr3_q_h(8) correspond to qdr3_q_h[16:9] and qdr3_q_h[7:0] respectively. 2 qdr3_d_h(0) qdr3_d_h(1) qdr3_d_h(2) qdr3_d_h(3) qdr3_d_h(4) qdr3_d_h(5) qdr3_d_h(6) qdr3_d_h(7) qdr3_d_h(9) qdr3_d_h(10) qdr3_d_h(11) qdr3_d_h(12) qdr3_d_h(13) qdr3_d_h(14) qdr3_d_h(15) qdr3_d_h(16) o data output bus. 16 qdr3_d_h(8) qdr3_d_h(17) o byte parity for data in qdr3_d_h(17)] and qdr3_d_h(8) correspond to qdr3_d_h[16:9] and qdr3_d_h[7:0] respectively. 2 qdr0_bws_l(0) qdr0_bws_l(1) qdr1_bws_l(0) qdr1_bws_l(1) qdr2_bws_l(0) qdr2_bws_l(1) qdr3_bws_l(0) qdr3_bws_l(1) o byte write enables. asserted to enable writing each byte during writes. 8 qdr0_rps_l(0) qdr0_rps_l(1) qdr1_rps_l(0) qdr1_rps_l(1) qdr2_rps_l(0) qdr2_rps_l(1) qdr3_rps_l(0) qdr3_rps_l(1) o read port enable. asserted to start a read. 8 table 6. sram signals (sheet 4 of 7) signal name i/o description number
intel ? ixp2800 and ixp2850 network processors signal description 28 datasheet qdr0_wps_l(0) qdr0_wps_l(1) qdr1_wps_l(0) qdr1_wps_l(1) qdr2_wps_l(0) qdr2_wps_l(1) qdr3_wps_l(0) qdr3_wps_l(1) o write port enable. asserted to start a write. 8 qdr0_a(0) qdr0_a(1) qdr0_a(2) qdr0_a(3) qdr0_a(4) qdr0_a(5) qdr0_a(6) qdr0_a(7) qdr0_a(8) qdr0_a(9) qdr0_a(10) qdr0_a(11) qdr0_a(12) qdr0_a(13) qdr0_a(14) qdr0_a(15) qdr0_a(16) qdr0_a(17) qdr0_a(18) qdr0_a(19) qdr0_a(20) qdr0_a(21) qdr0_a(22) qdr0_a(23) o address to srams. some addresses signals can be programmed to act as additional port enables (via csr control). refer to table 2 qdr address/rpe/wpe mapping . 24 qdr1_a(0) qdr1_a(1) qdr1_a(2) qdr1_a(3) qdr1_a(4) qdr1_a(5) qdr1_a(6) qdr1_a(7) qdr1_a(8) qdr1_a(9) qdr1_a(10) qdr1_a(11) qdr1_a(12) qdr1_a(13) qdr1_a(14) qdr1_a(15) qdr1_a(16) qdr1_a(17) qdr1_a(18) qdr1_a(19) qdr1_a(20) qdr1_a(21) qdr1_a(22) qdr1_a(23) o address to srams. some addresses signals can be programmed to act as additional port enables (via csr control). refer to table 2 qdr address/rpe/wpe mapping . 24 table 6. sram signals (sheet 5 of 7) signal name i/o description number
intel ? ixp2800 and ixp2850 network processors signal description datasheet 29 qdr2_a(0) qdr2_a(1) qdr2_a(2) qdr2_a(3) qdr2_a(4) qdr2_a(5) qdr2_a(6) qdr2_a(7) qdr2_a(8) qdr2_a(9) qdr2_a(10) qdr2_a(11) qdr2_a(12) qdr2_a(13) qdr2_a(14) qdr2_a(15) qdr2_a(16) qdr2_a(17) qdr2_a(18) qdr2_a(19) qdr2_a(20) qdr2_a(21) qdr2_a(22) qdr2_a(23) o address to srams. some addresses signals can be programmed to act as additional po rt enables (via csr control). refer to table 2 qdr address/rpe/wpe mapping . 24 qdr3_a(0) qdr3_a(1) qdr3_a(2) qdr3_a(3) qdr3_a(4) qdr3_a(5) qdr3_a(6) qdr3_a(7) qdr3_a(8) qdr3_a(9) qdr3_a(10) qdr3_a(11) qdr3_a(12) qdr3_a(13) qdr3_a(14) qdr3_a(15) qdr3_a(16) qdr3_a(17) qdr3_a(18) qdr3_a(19) qdr3_a(20) qdr3_a(21) qdr3_a(22) qdr3_a(23) o address to srams. some addresses signals can be programmed to act as additional po rt enables (via csr control). refer to table 2 qdr address/rpe/wpe mapping . 24 table 6. sram signals (sheet 6 of 7) signal name i/o description number
intel ? ixp2800 and ixp2850 network processors signal description 30 datasheet 3.2.3 media and switch fabric interface (msf) the media and switch fabric interface is used to interface the network processor to spi-4 phy chips, csix switch fabrics, and to other network processors. msf uses ieee lvds signaling levels for clock, data, control, and parity. the st atus channel and its clock use lvttl signaling., or alternatively, can be configured to use lvds i/o. vref_qdr0, vref_qdr1, vref_qdr2, vref_qdr3 i hstl reference voltage. 8 qdr0_zq(0) qdr0_zq(1) qdr1_zq(0) qdr1_zq(1) qdr2_zq(0) qdr2_zq(1) qdr3_zq(0) qdr3_zq(1) i impedance match. the qdrn_zq(0) pin for each channel should be connected to gnd through a 50-ohm resistor. the qdrn_zq(1) pins for each c hannel should be connected to vddq (1.5 v) through a 50-ohm resistor. internal circuits match the impedance of the output drivers to the value of this resistor. note : the nominal value is 50 ohms, and the resistor range is 25 to 65 ohms. the resistor tolerance is +/- 1%. 8 to ta l 321 table 6. sram signals (sheet 7 of 7) signal name i/o description number table 7. msf data signals (sheet 1 of 4) signal name i/o type spi-4 use csix use description number spi4_rclk_h, spi4_rclk_l i lvds rdclk txclk receive clock. used to register rdat, rctl, rpar and rprot. 2 spi4_rclk_ref_h, spi4_rclk_ref_l o lvds rclk_ref receive clock reference. buffered version of rclk. 2
intel ? ixp2800 and ixp2850 network processors signal description datasheet 31 spi4_rdat_h(0) spi4_rdat_h(1) spi4_rdat_h(2) spi4_rdat_h(3) spi4_rdat_h(4) spi4_rdat_h(5) spi4_rdat_h(6) spi4_rdat_h(7) spi4_rdat_h(8) spi4_rdat_h(9) spi4_rdat_h(10) spi4_rdat_h(11) spi4_rdat_h(12) spi4_rdat_h(13) spi4_rdat_h(14) spi4_rdat_h(15) spi4_rdat_l(0) spi4_rdat_l(1) spi4_rdat_l(2) spi4_rdat_l(3) spi4_rdat_l(4) spi4_rdat_l(5) spi4_rdat_l(6) spi4_rdat_l(7) spi4_rdat_l(8) spi4_rdat_l(9) spi4_rdat_l(10) spi4_rdat_l(11) spi4_rdat_l(12) spi4_rdat_l(13) spi4_rdat_l(14) spi4_rdat_l(15) i lvds rdat[15:0] txdata[15:0] receive data. from phy/switch fabric. 32 spi4_rpar_h spi4_rpar_l i lvds not used txpar receive parity. if not used (i.e, spi-4 mode) then this differential pair should be set to a logical 1 (spi4_rpar_h = 1 and spi4_rpar_l = 0). this is required for the dynamic training to function properly. 1 2 spi4_rctl_h spi4_rctl_l i lvds rctl txsof receive framing indicator. 2 spi4_rprot_h spi4_rprot_l i lvds rprot tprot receive protocol type. it indicates the protocol type, spi-4 or csix-l1, of the receive data, and can be tied statically low or high: 0 = spi-4, 1 = csix-l1. rprot must be driven to 1 during the entire cframe or 0 for the entire spi-4 burst. if not used (i.e, spi-4 mode) then this differential pair should be set to a logical 0 (spi4_rprot_h = 0 and spi4_rprot_l = 1). this is required for the dynamic training to function properly. 1. 2 spi4_rsclk o lvttl rsclk -- receive status clock. reference for rstat. 2 spi4_rstat(0) spi4_rstat(1) o lvttl rstat[1:0] -- receive fifo status. 2 table 7. msf data signals (sheet 2 of 4) signal name i/o type spi-4 use csix use description number
intel ? ixp2800 and ixp2850 network processors signal description 32 datasheet spi4_tclk_ref_h, spi4_tclk_ref_l i lvds tclk_ref transmit clock reference. buffered and used to generate tclk. 2 spi4_tclk_h, spi4_tclk_l o lvds tdclk rxclk transmit clock. used to register tdat, tctl, tpar, and tprot. 2 spi4_tdat_h(0) spi4_tdat_h(1) spi4_tdat_h(2) spi4_tdat_h(3) spi4_tdat_h(4) spi4_tdat_h(5) spi4_tdat_h(6) spi4_tdat_h(7) spi4_tdat_h(8) spi4_tdat_h(9) spi4_tdat_h(10) spi4_tdat_h(11) spi4_tdat_h(12) spi4_tdat_h(13) spi4_tdat_h(14) spi4_tdat_h(15) spi4_tdat_l(0) spi4_tdat_l(1) spi4_tdat_l(2) spi4_tdat_l(3) spi4_tdat_l(4) spi4_tdat_l(5) spi4_tdat_l(6) spi4_tdat_l(7) spi4_tdat_l(8) spi4_tdat_l(9) spi4_tdat_l(10) spi4_tdat_l(11) spi4_tdat_l(12) spi4_tdat_l(13) spi4_tdat_l(14) spi4_tdat_l(15) o lvds tdat[15:0] rxdata[15:0] transmit data to phy/switch fabric. 32 spi4_tctl_h, spi4_tctl_l o lvds tctl rxsof transmit framing indicator. 2 spi4_tpar_h, spi4_tpar_l o lvds not used rxpar transmit parity. 2 spi4_tprot_h, spi4_tprot_l o lvds tprot rprot transmit protocol type. it indicates the protocol type, spi-4 or csix-l1, of the transmit data, and can be ignored if not needed: 0 = spi-4, 1 = csix-l1. tprot is driven to 1 during the entire cframe or 0 for the entire spi-4 burst. 2 spi4_tsclk i lvttl tsclk -- transmit status clock. used to register tstat. 1 spi4_tstat(0), spi4_tstat(1) i lvttl tstat[1:0] -- transmit fifo status. 2 spi4_preemp i lvttl impedance match. in normal operation, should be tied to logical 0. 1 table 7. msf data signals (sheet 3 of 4) signal name i/o type spi-4 use csix use description number
intel ? ixp2800 and ixp2850 network processors signal description datasheet 33 the next group in table 8 is used to communicate flow cont rol information between two network processors. spi4_zq2 spi4_zq1 i/o impedance match. the zq1 and zq2 pins should be connected together through a 100-ohm resistor. internal circuitry matches the impedance of the internal termination resistors on all lvds input pairs to value of this resistor. 2 to ta l 95 1. floating and unused lvds inputs should be terminated, as specified in section 3.3 . table 7. msf data signals (sheet 4 of 4) signal name i/o type spi-4 use csix use description number table 8. msf flow control signals (sheet 1 of 2) signal name i/o type spi-4 use 1 (note 1) csix use description number fc_txcclk_h, fc_txcclk_l o lvds rsclk txcclk flow control egress clock. reference for txcsrb, txcdat, txcsof, txcpar, and rxcfc. fifo status clock for spi-4. 2 fc_txcsrb_h, fc_txcsrb_l o lvds -- txcsrb flow control egress serialized ready bits. 2 fc_txcdat_h(0) fc_txcdat_h(1) fc_txcdat_h(2) fc_txcdat_h(3) fc_txcdat_l(0) fc_txcdat_l(1) fc_txcdat_l(2) fc_txcdat_l(3) o lvds rstat[1:0] txcdat[3:0] flow control egress data ? csix. receive fifo status ? spi-4. note : when used in lvds rstat mode, only fc_txcdat_h/_l[1:0] are used. fc_txcdat_h/_l[3:2] are unused. 8 fc_txcsof_h, fc_txcsof_l o lvds -- txcsof flow control egress start of frame. 2 fc_txcpar_h, fc_txcpar_l o lvds -- txcpar flow control egress parity. 2 fc_txcfc_h, fc_txcfc_l i lvds -- txcfc flow control egress fifo full. this signal is received relative to txcclk, but is treated as asynchronous; also used during flow control pin training. 2 2 fc_rxcclk_h, fc_rxcclk_l i lvds tsclk rxcclk transmit status ingress clock. used to register rxcsrb, rxcdat, rxcsof, and rxcpar. fifo status clock for spi-4. 2 2 fc_rxcsrb_h, fc_rxcsrb_l i lvds -- rxcsrb flow control ingress serialized ready bits. 2 2
intel ? ixp2800 and ixp2850 network processors signal description 34 datasheet 3.2.4 pci the pci bus can be used to interface to industry standard i/o devices, or to a host processor; see table 9 for a list of signals. pci signaling levels are defined in pci local bus specification, version 2.2*. fc_rxcdat_h(0) fc_rxcdat_h(1) fc_rxcdat_h(2) fc_rxcdat_h(3) fc_rxcdat_l(0) fc_rxcdat_l(1) fc_rxcdat_l(2) fc_rxcdat_l(3) i lvds tstat[1:0] rxcdat[3:0] flow control ingress data ? csix. transmit status ? spi-4. note : when used in lvds tstat mode, only fc_rxcdat_h/_l[1:0] are used. fc_rxcdat_h/_l[3:2] are unused. 2 8 fc_rxcsof_h, fc_rxcsof_l i lvds rxcsof flow control ingress start of frame. 2 2 fc_rxcpar_h, fc_rxcpar_l i lvds rxcpar flow control ingress parity. if not used, then this differential pair should be set to a logical 0 (fc_rxcpar_h = 0 and fc_rxcpar_l = 1). this is required for the dynamic training to function properly. 2 2 fc_rxcfc_h, fc_rxcfc_l o lvds rxcfc flow control ingress fifo full. 2 fc_zq(1) fc_zq(2) i/o impedance match. the zq1 and zq2 pins should be connected together through a 100-ohm resistor. 2 vreflo vreflo i reference voltage. 2 vrefhi vrefhi i reference voltage. 2 fc_preemp i lvttl impedance match. in normal operation, should be tied to logical 0. 1 to ta l 43 1. spi-4 can use lvds status channel in place of lvttl pins defi ned in table 5. lvds pins are enabled by msf_rx_control[rstat_se lect] and msf_tx_control[tstat_select]. 2. floating and unused lvds inputs sh ould be terminated, as specified in section 3.3 . table 8. msf flow contro l signals (sheet 2 of 2) signal name i/o type spi-4 use 1 (note 1) csix use description number
intel ? ixp2800 and ixp2850 network processors signal description datasheet 35 table 9. pci signals (sheet 1 of 3) signal name i/o description number pci_ad(0) pci_ad(1) pci_ad(2) pci_ad(3) pci_ad(4) pci_ad(5) pci_ad(6) pci_ad(7) pci_ad(8) pci_ad(9) pci_ad(10) pci_ad(11) pci_ad(12) pci_ad(13) pci_ad(14) pci_ad(15) pci_ad(16) pci_ad(17) pci_ad(18) pci_ad(19) pci_ad(20) pci_ad(21) pci_ad(22) pci_ad(23) pci_ad(24) pci_ad(25) pci_ad(26) pci_ad(27) pci_ad(28) pci_ad(29) pci_ad(30) pci_ad(31) pci_ad(32) pci_ad(33) pci_ad(34) pci_ad(35) pci_ad(36) pci_ad(37) pci_ad(38) pci_ad(39) pci_ad(40) pci_ad(41) pci_ad(42) pci_ad(43) pci_ad(44) pci_ad(45) pci_ad(46) pci_ad(47) pci_ad(48) pci_ad(49) pci_ad(50) pci_ad(51) pci_ad(52) pci_ad(53) pci_ad(54) i/o address/data bus 64
intel ? ixp2800 and ixp2850 network processors signal description 36 datasheet pci_ad(55) pci_ad(56) pci_ad(57) pci_ad(58) pci_ad(59) pci_ad(60) pci_ad(61) pci_ad(62) pci_ad(63) pci_cbe_l(0) - pci_cbe_l(7) i/o cycle status/byte enable 8 pci_par i/o parity data 1 pci_par64 i/o parity data 1 pci_frame_l i/o frame 1 pci_irdy_l i/o initiator ready 1 pci_trdy_l i/o target ready 1 pci_stop_l i/o stop 1 pci_devsel_l i/o device select 1 pci_idsel i initialization device select 1 pci_req64_l i/o 64-bit request 1 pci_ack64_l i/o 64-bit acknowledge 1 pci_perr_l i/o parity error 1 pci_serr_l i/o d system error 1 pci_req_l(0) i/o bus request. input from external bus master when internal pci arbiter is used. output to external arbiter when internal arbiter is not used. 1 pci_req_l(1) i bus request. input from external bus master when internal pci arbiter is used. 1 pci_gnt_l(0) i/o bus grant. output to external bus master when ixp2800/ixp2850 arbiter is used. input to ixp2800/ixp2850 from external pci arbiter when internal arbiter is not used. 1 pci_gnt_l(1) o bus grant. output to external bus master when internal pci arbiter is used. 1 pci_inta_l i/o d pci interrupt. input when ixp2800/ixp2850 is host; output when ixp2800/ixp2850 is not host. 1 pci_intb_l i interrupt 1 pci_rst_l i/o bus reset 1 pci_clk i bus clock 1 pci_m66en i 66-mhz enable 1 table 9. pci signals (sheet 2 of 3) signal name i/o description number
intel ? ixp2800 and ixp2850 network processors signal description datasheet 37 3.2.5 slowport signals the slowport is used to interfa ce to asynchronous devices. typica lly this will be a flash rom (boot rom) and maintenance port of mac devices. slowport signals use lvttl signaling levels (see table 10 ). pci_zq1, pci_zq2 i/o impedance match. the pci_zq1 pin should be tied to vss through a 31.6-ohm resistor. internal circuits match the impedance of the output drivers to the value of this resistor when the outputs are driving a high logic level. note : the nominal value for zq1 is 31.6 ohms, and the resistor range is 30.1 to 34 ohms. the resistor tolerance should be +/- 1%. the pci_zq2 pin should be connected to vcc3.3 through a 28-ohm resistor. internal circuits match the impedance of the output drivers to the value of this resistor when the outputs are driving a low logic level. note : the nominal value for zq2 is 28 ohms, and the resistor range is 27.4 to 31.6 ohms. the resistor tolerance should be +/- 1%. 2 to ta l 95 table 9. pci signals (sheet 3 of 3) signal name i/o description number table 10. slowport signals signal name i/o description number sp_clk o clock. 1 sp_wr_l o write strobe. 1 sp_rd_l o read strobe. 1 sp_ad(0) sp_ad(1) sp_ad(2) sp_ad(3) sp_ad(4) sp_ad(5) sp_ad(6) sp_ad(7) i/o multiplexed address and data. 8 sp_ack_l i acknowledge signal. 1 sp_cs_l(0), sp_cs_l(1) o device selects. 2 sp_ale_l o address latch enable. 1 sp_cp/sp_a0 o latch enable for 16 or 32-bit data bus devices. address [0] for 8-bit devices. 1 sp_oe_l o output enable. 1 sp_dir/sp_a1 o data transaction direction. low for read, high for write. address [1] for 8-bit devices. 1 to ta l 18
intel ? ixp2800 and ixp2850 network processors signal description 38 datasheet 3.2.6 gpio signals gpio are general-purpose i/o sign als. they can be used for slow speed, software-controlled i/o such as leds and input switches. they are also three-stated duri ng reset to bring configuration information into the network processor; the in formation is latched at the deassertion of clk_nreset. the gpio signals use lvttl signaling levels ? see table 11 . 3.2.7 serial port signals the serial port is an rs-232 compatible uart used for debug and diagnostics. see table 12 for the serial port signals. 3.2.8 clock and reset signals all clock and reset signals, except for cl k_ref_clk_h and clk_ref_clk_l, use lvttl signaling levels. table 13 lists the clock and reset signals. table 11. gpio signals signal name i/o description number gpio(0) gpio(1) gpio(2) gpio(3) gpio(4) gpio(5) gpio(6) gpio(7) i/o general purpose i/o. 8 to ta l 8 table 12. serial port signals signal name i/o description number sr_rx i receive data into the uart. 1 sr_tx o transmit data from the uart. 1 to ta l 2 table 13. clock signals (sheet 1 of 2) signal name i/o description number clk_ref_clk_h clk_ref_clk_l i pll clock reference (lvds). the clk_ref_clk input pair does not have active on-die termination. this input pair must be terminated on the pcb with a 100-ohm resistor between the clk_ref_clk_h and clk_ref_clk_l pins. 2 clk_phase_ref o reference clock phase delay output. in test mode, this output pin determines the ref_clk_lvds input buffer delay. in normal operation, this pin outputs the programmed dram_n clock frequency from the on-board pll divided by 2, which is then used as the reference clock for the direct rambus clock generator (drcg). 1 clk_stop i pll stop test mode. tie to logical 0 in normal operation. 1
intel ? ixp2800 and ixp2850 network processors signal description datasheet 39 3.2.9 power supply pins clk_pll_byp i pll bypass test mode. when asserted, the ixp2800/ixp2850 uses the external clock inputs (clk_ref_clk in place of p ll clocks. this pin should be tied to logical 0 during normal operation. 1 clk_nreset i master reset input. active low. all configuration strap options are latched on the deassertion of this signal. th is signal must be toggled even in pci boot mode to latch the configuration straps options. 1 clk_nreset_out o reset output. active low. this output is controlled by configuration pin sp_ad[7] listed in table 16 configuration pins . 1 to ta l 7 table 14. power supply pins (sheet 1 of 2) signal names total pin descriptions vcc_clk 1 2.5 v supply. may be tied to the same board level supply as vcc25v. vcc_fuse 4 1.35/1.3/1.2 v supply for the fuse logic. may be tied to the same board level supply as vcc. the fuse circuit suppl y has been isolated from vcc because this supply must be elevated during the fuse programming sequence, which only occurs during final manufactur ing test (not user accessible). vrefhi_clk 1 these pins shoul d be tied to vss (logical 0). vreflo_clk 1 these pins shoul d be tied to vss (logical 0). vcc_pll 1 1.35/1.3/1.2 v supply for the on-chip pll. if the board level supply is exceptionally clean, this supply could be tied to the same board level supply as vcc. given that most applications wi tness substantial noise on vcc, the vcc_pll should be generated by filtering vcc with an lc network (see figure 10 ). vcc 78 core power supply. vss 371 core ground. vcc25v 28 spi-4 supply (also for pci). vcca_fc 1 dll power. should be generated by filtering vcc with an lc network (see figure 10 ). vcca_spi4 1 dll power. should be generated by filtering vcc with an lc network (see figure 10 ). vrefhi 2 spi-4/flow reference voltage. vreflo 2 spi-4/flow reference voltage. vcc33 4 gpio, jtag, sp power. vcc33_pci 12 pci power supply. vddq 101 qdr power supply. pas0_vcca 1 dll power. should be generated by filtering vcc with an lc network (see figure 10 ). table 13. clock signals (sheet 2 of 2) signal name i/o description number
intel ? ixp2800 and ixp2850 network processors signal description 40 datasheet 3.2.10 test and jtag signals jtag is the ieee 1149.1 test access port. the jt ag input signals have a weak pullup resistor internal to the chip, so that any input that is not terminated, is interpreted as a high. other test signals are network pro cessor specific, for manu facturing use only. see table 15 . pas1_vcca 1 dll power. should be generated by filtering vcc with an lc network (see figure 10 ). pas2_vcca 1 dll power. should be generated by filtering vcc with an lc network (see figure 10 ). pas3_vcca 1 dll power. should be generated by filtering vcc with an lc network (see figure 10 ). vref_qdr0 2 qdr reference voltage. vref_qdr1 2 qdr reference voltage. vref_qdr2 2 qdr reference voltage. vref_qdr3 2 qdr reference voltage. vccr 14 rdram core processor. vccra 6 rdram clean power. should be generated by filtering vcc with an lc network (see figure 10 ). vccrio 9 rdram i/o power. par0_padvrefa 1 rdram reference voltage. par0_padvrefb 1 rdram reference voltage. par1_padvrefa 1 rdram reference voltage. par1_padvrefb 1 rdram reference voltage. par2_padvrefa 1 rdram reference voltage. par2_padvrefb 1 rdram reference voltage. total power supply pins 655 table 14. power supply pins (sheet 2 of 2) signal names total pin descriptions table 15. test and jtag signals (sheet 1 of 2) signal name i/o description number jtag_tck i test interface reference clock that times all the transfers on the jtag test interface. 1 jtag_tms i test interface mode select. tms causes state transitions in the test access port (tap) controller. 1 jtag_tdi i test interface data input. tdi is the serial input through which jtag instructions and test data enter the jtag interface. 1 jtag_tdo oz test interface data output. tdo is the serial output through which test instructions and dat a from the test logic leave the network processor. 1
intel ? ixp2800 and ixp2850 network processors signal description datasheet 41 3.2.11 configuration pins these pins are tied statically high or low throug h a resistor to provide configuration information into the network processor at reset. for all bu t cfg_rst_dir, these pi ns are used for other purposes after reset. for those pins, the configur ation information is sampled at the deassertion (rising) edge of clk_nreset. the values sampled can be read in the strap_options register. jtag_trst i test interface reset. when asserted low, the tap controller is asynchronously forced to enter a reset state, which in turn asynchronously initializes other test logic. this pin must be driven or held low to achieve normal device operation. 1 test_scan_clk_a test_scan_clk_b i scan chain clocks. these pins are used to input the scan clocks used during scan test ing and must be tied to a logical 1 in a system environment. 2 test_scan_en i scan chain enable. this input pin places the chip in scan test mode when asserted, and is only used during scan testing. this pin should be tied to a logical 0 in a system environment. 1 test_scan_mode i strobe test mode pins. this input pin is used to latch values into the test mode register and is used in conjunction with interrupt_mode, sp_ad[7:0] and gpio[3:0] during scan testing. this pin should be tied to a logical 0 in a system environment. note : for the a stepping of the device, the name of this pin was test_clk. the name was changed in the b stepping; however, the functional ity of the pin is identical. 1 test_diode_a i thermal diode anode. this pin should be tied to a logical 0 if the pin is not being used. 1 interrupt_mode i 1?selects signals from the gpio and slowport pins to be routed to the test box instead of the gpio and slowport ports, and sets the jtag_tms, test_scan_mode, jtag_tdi, and test_scan_en pins to operate in their test mode. 0?these pins have their normal function. this pin should be tied to a logical 0 in a system environment. note : for the a stepping of the device, the name of this pin was test_mode_load. the name was changed in the b stepping; however, the functional ity of the pin is identical. 1 test_diode_c i thermal diode cathode. this pin should be tied to a logical 0 if the pin is not being used. 1 clk_rst_dis i this is a test mode control input to the ixp2800/ixp2850 and is only used during scan te sting. this signal must be tied to a logical 0 in a system environment. to ta l 12 table 15. test and jtag signals (sheet 2 of 2) signal name i/o description number
intel ? ixp2800 and ixp2850 network processors signal description 42 datasheet table 16. configuration pins pin configuration function description clk_cfg_rst_dir cfg_rst_dir determines direction of pci_rst# signal: ? 1?network processor is the host supporting central functions. pci_rst# is an output. nreset is used as reset input. ? 0?external pci host supporting central functions. pci_rst# is an input. gpio[0] cfg_prom_boot indicates if boot rom is present: ? 0?no boot rom; host must download boot image into dram ? 1?boot rom is present gpio[1] cfg_pci_boot_host indicates if the host or intel xscale ? core will configure pci devices: ? 0?external host ? 1?ixp2800 gpio[2] cfg_pci_arb pci arbiter used: ? 0?ixp2800/ixp2850 is not the arbiter ? 1?ixp2800/ixp2850 is the arbiter gpio[4:3] cfg_pci_dwin[1:0] select dram bar window size: ? 11?1024 mbyte ? 10?512 mbyte ? 01?256 mbyte ? 00?128 mbyte gpio[6:5] cfg_pci_swin[1:0] select sram bar window size: ? 11?256 mbyte ? 10?128 mbyte ? 01?64 mbyte ? 00?32 mbyte sp_ad[5:0] cfg_pll_mult[5:0] select pll multiplier: ? 0x10?16 ? 0x12?18 ? ... ? 0x30?48 note : only even multipliers between 0x16 - 0x48 are supported. sp_ad[6] cfg_msf_freq_sel select source of msf tx clock: ? 0?tclk_ref input pin ? 1?internally generated clock sp_ad[7] reset_out_strap ? 1?nreset_out is removed after pll locks. ? 0?nreset_out is removed by software using bit ixp_reset0[17].
intel ? ixp2800 and ixp2850 network processors signal description datasheet 43 3.2.12 pin state during reset table 17 defines the state of both the output (o) and bidirectional (ts) pins during reset. table 17. pin state during reset (sheet 1 of 4) function pin name initial values comment sram qdrn_a_h[23:0] output, low sram qdrn_rps_l[1:0] output, high sram qdrn_wps_l[1:0] output, high sram qdrn_bws_l[1:0] output, high sram qdrn_k_l[1:0] qdrn_k_h[1:0] clock out sram qdrn_c_l[1:0] qdrn_c_h[1:0] clock out sram qdrn_d_h[17:0] output, low sram qdrn_cin_l[1:0] qdrn_cin_h[1:0] clock in qdrn_cin_l(1) and qdrn_cin_h(1) input pad outputs are not connected internally. sram qdrn_q_h[17:0] input sram qdrn_vref[2:0] 0.75 v sram qdrn_zq[0] pull down to gnd through a 50-ohm resistor. sram qdrn_zq[1] pull up to 1.5 v through a 50-ohm resistor. sram vddq 1.5 v rdram rdrn_dqa rsl 0 1.8 v pin is to be 1.8 v by the external terminator when rsl 0. rdram rdrn_dqb rsl 0 pin is to be 1.8 v by the external terminator when rsl 0. rdram rdrn_rq rsl 0 pin is to be 1.8 v by the external terminator when rsl 0. rdram rdrn_ctm, rdrn_ctmn clock rdram rdrn_cfm, rdrn_cfmn clock cfm and cfmn are directly connected to ctm and ctmn, respectively, inside the chip. rdram rdrn_sio output, low rdram rdrn_sck output, high rdram rdrn_cmd output, low rdram rdrn_synclkm clock rdram rdrn_pclkn clock rdram vss gnd
intel ? ixp2800 and ixp2850 network processors signal description 44 datasheet pci pci_ad[31:0] low = central high = non-central central function: ? during pci reset (pci_rst_l =0), the network processor needs to drive pci_ad[31:0] and pci_be[3:0], pci_par to low.the rest of the i/o devices will be in three states. ? after pci_rst_l is deasserted, the network processor will drive these i/o devices (pci_ad[31:0], pci_be[3:0], and pci_par) to three states unless the network processor owns the grant. non-central function: ? during pci reset (pci_rst_l =0), the network processor needs to drive all of the i/o devices to three states. once the network processor owns the bus (grant), the network processor needs to drive these i/o devices pci_ad[31:0], pci_be[3:0], and pci_par to known values. pci pci_ad[63:32] high-z need external pullup. pci pci_cbe_l[3:0] low = central high = non-central central function: ? during pci reset (pci_rst_l =0), the network processor needs to drive pci ad[31:0] and pci_be[3:0], pci_par to low.the rest of the i/o devices will be in three states. ? after pci_rst_l is deasserted, the network processor will drive these i/o devices (pci_ad[31:0], pci_be[3:0], and pci_par) to three states unless the network processor owns the grant. non-central function: ? during pci reset (pci_rst_l =0), the network processor needs to drive all the i/o devices to three states. once the network processor owns the bus (grant), the network processor needs to drive these i/o devices pci_ad[31:0], pci_be[3:0], and pci_par to known values. pci pci_cbe_l7:4 high-z need external pullup. table 17. pin state during reset (sheet 2 of 4) function pin name initial values comment
intel ? ixp2800 and ixp2850 network processors signal description datasheet 45 pci pci_par low = central high = non-central central function : ? during pci reset (pci_rst_l =0), the network processor needs to drive pci ad[31:0] and pci_be[3:0], pci_par. in addition, the rest of the i/o devices will be in three states. ? after pci_rst_l is deasserted, the network processor will drive these i/o devices (pci_ad[31:0], pci_be[3:0], pci_par) to three states unless the network processor owns the grant. non-central function: ? during pci reset (pci_rst_l =0), the network processor needs to drive all the i/o devices to three states. once the network processor owns the bus (grant), the network processor needs to drive these i/o devices pci_ad[31:0], pci_be[3:0], and pci_par to known values. pci pci_par64 high-z need external pullup. pci pci_frame_l high-z pci pci_irdy_l high-z pci pci_trfy_l high-z pci pci_stop_l high-z pci pci_devsel_l high-z pci pci_idsel high-z pci pci_req64_l low = central high-z = non_central central function : during pci reset (pci_rst_l =0), the network processor needs to drive pci_req64l low. pci pci_ack64_l high-z pci pci_perr_l high-z pci pci_serr high-z pci pci_req_l(0) high-z pci pci_req_l(1) high-z pci pci_gnt_l(0) high-z pci pci_gnt_l(1) high-z pci pci_inta_l high-z pci pci_intb_l high-z pci pci_rst_l input pci pci_clk input pci pci_m66en input pci pci_zq1, pci_zq2 input gpio gpio[7:0] high z table 17. pin state during reset (sheet 3 of 4) function pin name initial values comment
intel ? ixp2800 and ixp2850 network processors signal description 46 datasheet serial port sr_rx input serial port sr_tx low slowport sp_cp, sp_dir low slowport sp_ad[7:0] high z slowport sp_clk high slowport sp_wr_l high slowport sp_rd_l high slowport sp_ack_l high slowport sp_cs_ln high slowport sp_ale_l high slowport sp_oe_l high clock signals clk_phase_ref outputs the clock signal driven from core. clock signals clk_nreset_out during reset, the value is 0; once reset goes away, the value changes to 1 after some delay. clock signals clk_ref_clk_h, clk_ref_clk_l input clock signals clk_stop input clock signals clk_pll_byp input clock signals clk_nreset input msf data signals spi4_rstat[1:0] output, high msf data signals spi4_rctl_ref, spi4_tclk high z msf data signals all other pins output, low msf flow control signals fc_txcclk outputs the clock signal presented by the core logic. msf flow control signals all other pins output, low test and jtag signals all pins high z table 17. pin state during reset (sheet 4 of 4) function pin name initial values comment
intel ? ixp2800 and ixp2850 network processors signal description datasheet 47 3.2.13 ball assignment this section describes the network processor ball assignment and lists the pins according to location (numeric) and in alphabetic order. 3.2.13.1 pins listed in numeric order table 18 lists the network processor pins in order of location (numeric), showing the location code and name of each pin.
intel ? ixp2800 and ixp2850 network processors signal description 48 datasheet table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 1 of 19) fcbga location pin name fcbga location pin name a1 n/c b1 rdr0_cmd a2 rdr0_dqb[8] b2 vss a3 rdr0_dqb[5] b3 vss a4 rdr0_dqb[2] b4 vss a5 rdr0_rq[0] b5 vss a6 rdr0_rq[3] b6 vss a7 rdr0_rq[6] b7 vss a8 rdr0_ctmn b8 vss a9 rdr0_ctm b9 vss a10 rdr0_dqa[2] b10 vss a11 rdr0_dqa[5] b11 vss a12 rdr0_dqa[6] b12 vss a13 rdr1_cmd b13 rdr1_sclkn a14 rdr1_dqb[8] b14 vss a15 rdr1_dqb[7] b15 vss a16 rdr1_dqb[4] b16 vss a17 rdr1_rq[0] b17 vss a18 n/c b18 rdr1_rq[1] a19 n/c b19 vss a20 n/c b20 rdr1_rq[5] a21 rdr1_ctmn b21 vss a22 rdr1_ctm b22 vss a23 rdr1_dqa[0] b23 vss a24 rdr1_dqa[2] b24 vss a25 rdr1_dqa[6] b25 vss a26 rdr2_sio b26 vss a27 rdr2_dqb[8] b27 vss a28 rdr2_dqb[7] b28 vss a29 rdr2_dqb[4] b29 vss a30 rdr2_rq[0] b30 vss a31 rdr2_rq[1] b31 vss a32 rdr2_rq[4] b32 vss a33 rdr2_ctmn b33 vss a34 rdr2_ctm b34 vss a35 rdr2_dqa[0] b35 vss a36 rdr2_dqa[3] b36 vss a37 vss b37 rdr2_dqa[8]
intel ? ixp2800 and ixp2850 network processors signal description datasheet 49 c1 vss d1 rdr0_sio c2 vss d2 rdr0_pclkm c3 rdr0_dqb[6] d3 vss c4 rdr0_dqb[3] d4 vss c5 rdr0_dqb[1] d5 vss c6 rdr0_rq[2] d6 vss c7 rdr0_rq[5] d7 vss c8 rdr0_cfmn d8 vss c9 rdr0_cfm d9 vss c10 rdr0_dqa[1] d10 vss c11 rdr0_dqa[4] d11 vss c12 rdr0_dqa[7] d12 vss c13 vss d13 rdr1_sck c14 vss d14 rdr1_pclkm c15 rdr1_dqb[5] d15 vss c16 rdr1_dqb[2] d16 vss c17 rdr1_dqb[1] d17 vss c18 vss d18 rdr1_rq[2] c19 rdr1_rq[3] d19 vss c20 vss d20 rdr1_rq[7] c21 rdr1_cfmn d21 vss c22 rdr1_cfm d22 vss c23 rdr1_dqa[1] d23 vss c24 rdr1_dqa[4] d24 vss c25 rdr1_dqa[8] d25 vss c26 rdr2_sck d26 rdr2_sclkn c27 vss d27 rdr2_pclkm c28 rdr2_dqb[6] d28 vss c29 rdr2_dqb[3] d29 vss c30 rdr2_dqb[1] d30 vss c31 rdr2_rq[2] d31 vss c32 rdr2_rq[5] d32 vss c33 rdr2_cfmn d33 vss c34 rdr2_cfm d34 vss c35 rdr2_dqa[1] d35 vss c36 rdr2_dqa[4] d36 vss c37 vss d37 rdr2_dqa[6] table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 2 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description 50 datasheet e1 vss f1 rdr0_sck e2 vss f2 rdr0_sclkn e3 rdr0_dqb[7] f3 vss e4 rdr0_dqb[4] f4 vss e5 rdr0_dqb[0] f5 vss e6 rdr0_rq[1] f6 par0_padvrefb e7 rdr0_rq[4] f7 vss e8 rdr0_rq[7] f8 vss e9 vss f9 par0_padvrefa e10 rdr0_dqa[0] f10 vss e11 rdr0_dqa[3] f11 vss e12 rdr0_dqa[8] f12 vss e13 vss f13 vss e14 vss f14 rdr1_sio e15 rdr1_dqb[6] f15 vss e16 rdr1_dqb[3] f16 vss e17 rdr1_dqb[0] f17 vss e18 vss f18 par1_padvrefb e19 rdr1_rq[4] f19 vss e20 vss f20 par1_padvrefa e21 rdr1_rq[6] f21 vss e22 vss f22 vss e23 rdr1_dqa[3] f23 vss e24 rdr1_dqa[5] f24 vss e25 rdr1_dqa[7] f25 vss e26 rdr2_cmd f26 vss e27 vss f27 vss e28 rdr2_dqb[5] f28 vss e29 rdr2_dqb[0] f29 vss e30 rdr2_dqb[2] f30 vss e31 rdr2_rq[3] f31 par2_padvrefb e32 rdr2_rq[6] f32 vss e33 rdr2_rq[7] f33 vss e34 vss f34 par2_padvrefa e35 rdr2_dqa[2] f35 vss e36 rdr2_dqa[5] f36 vss e37 vss f37 rdr2_dqa[7] table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 3 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description datasheet 51 g1 vccrio h1 vcc33_pci g2 vss h2 pci_ad[15] g3 vccrio h3 pci_ad[9] g4 vccr h4 vss g5 vccra h5 pci_ad[42] g6 vss h6 pci_ad[38] g7 vccr h7 vcc33_pci g8 vccr h8 pci_ad[35] g9 vccra h9 pci_ad[33] g10 vccr h10 vss g11 vccrio h11 pci_ad[53] g12 vccr h12 pci_ad[59] g13 vss h13 vcc33_pci g14 vss h14 vss g15 vccrio h15 pci_ad[47] g16 vss h16 vcc33_pci g17 vccrio h17 vss g18 vss h18 vss g19 vccra h19 sp_ad[0] g20 vccr h20 test_scan_en g21 vccr h21 gpio[7] g22 vccra h22 sr_rx g23 vccr h23 vss g24 vccrio h24 sp_rd_l g25 vccr h25 sp_ad[1] g26 vccrio h26 vcc33 g27 vss h27 gpio[1] g28 vccrio h28 sp_ad[5] g29 vccr h29 vrefhi_clk g30 vccra h30 vreflo_clk g31 vss h31 vss g32 vccr h32 qdr3_q_h[9] g33 vccr h33 qdr3_q_h[10] g34 vccra h34 vddq g35 vccr h35 vddq g36 vccrio h36 vref_qdr3 g37 vccr h37 vref_qdr3 table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 4 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description 52 datasheet j1 pci_ad[29] k1 pci_gnt_l[0] j2 pci_par k2 vss j3 pci_ad[10] k3 pci_ad[20] j4 pci_ad[8] k4 pci_ad[13] j5 pci_ad[61] k5 pci_ad[5] j6 pci_ad[56] k6 pci_ad[1] j7 pci_ad[55] k7 pci_cbe_l[7] j8 pci_ad[48] k8 pci_par64 j9 pci_ad[44] k9 pci_ad[54] j10 pci_ad[40] k10 pci_ad[45] j11 pci_ad[34] k11 pci_ad[32] j12 pci_ad[2] k12 pci_ad[25] j13 vcc25v k13 pci_ad[11] j14 pci_ack64_l k14 pci_ad[51] j15 pci_cbe_l[4] k15 pci_ad[57] j16 pci_ad[39] k16 pci_ad[49] j17 vcc25v k17 vss j18 pci_ad[41] k18 pci_ad[36] j19 vcc_clk k19 vss j20 sp_cs_l[1] k20 sp_ad[4] j21 gpio[3] k21 jtag_trst j22 jtag_tms k22 clk_stop j23 jtag_tdi k23 clk_cfg_rst_dir j24 sp_ad[7] k24 gpio[5] j25 sp_ack_l k25 gpio[0] j26 gpio[2] k26 sr_tx j27 gpio[4] k27 sp_ad[2] j28 sp_ad[6] k28 sp_dir j29 test_diode_a k29 test_diode_c j30 vss k30 vss j31 vddq k31 qdr3_q_h[7] j32 qdr3_q_h[6] k32 vss j33 qdr3_q_h[11] k33 qdr3_q_h[12] j34 vss k34 vddq j35 qdr3_q_h[5] k35 qdr3_q_h[4] j36 qdr3_q_h[13] k36 vddq j37 vss k37 qdr3_d_h[9] table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 5 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description datasheet 53 l1 pci_gnt_l[1] m1 vss l2 pci_ad[28] m2 pci_inta_l l3 vcc33_pci m3 pci_idsel l4 pci_ad[17] m4 pci_ad[22] l5 vss m5 pci_ad[31] l6 pci_ad[21] m6 pci_ad[30] l7 pci_trdy_l m7 pci_ad[16] l8 vcc33_pci m8 pci_ad[7] l9 pci_ad[0] m9 pci_ad[3] l10 pci_ad[60] m10 pci_ad[62] l11 vss m11 pci_ad[46] l12 pci_m66en m12 pci_ad[37] l13 pci_cbe_l[0] m13 vcc25v l14 vcc33_pci m14 pci_ad[14] l15 pci_stop_l m15 pci_cbe_l[6] l16 pci_ad[63] m16 vss l17 pci_ad[43] m17 vcc33_pci l18 pci_ad[50] m18 vcc25v l19 vss m19 vss l20 clk_nreset m20 jtag_tck l21 clk_nreset_out m21 test_scan_mode l22 vcc33 m22 interrupt_mode l23 vss m23 sp_cp l24 gpio[6] m24 sp_cs_l[0] l25 sp_ale_l m25 jtag_tdo l26 sp_wr_l m26 sp_clk l27 sp_ad[3] m27 sp_oe_l l28 test_scan_clk_a m28 test_scan_clk_b l29 vcc33 m29 clk_phase_ref l30 qdr3_q_h[8] m30 qdr3_q_h[3] l31 vddq m31 qdr3_q_h[15] l32 qdr3_q_h[14] m32 vss l33 qdr3_cin_h[1] m33 qdr3_cin_h[0] l34 vss m34 vddq l35 vss m35 qdr3_cin_l[1] l36 qdr3_d_h[10] m36 vddq l37 vss m37 qdr3_d_h[11] table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 6 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description 54 datasheet n1 spi4_rstat[0] p1 vcc25v n2 spi4_rsclk p2 vss n3 spi4_rstat[1] p3 spi4_tstat[1] n4 pci_cbe_l[3] p4 spi4_tsclk n5 pci_devsel_l p5 spi4_tstat[0] n6 pci_req_l[1] p6 pci_ad[26] n7 pci_ad[19] p7 pci_irdy_l n8 pci_zq1 p8 pci_serr_l n9 pci_ad[4] p9 vss n10 pci_cbe_l[5] p10 pci_ad[6] n11 pci_ad[58] p11 vcc33_pci n12 pci_ad[52] p12 pci_req64_l n13 vcc p13 vss n14 vss p14 vcc n15 vcc p15 vss n16 vss p16 vcc n17 vcc p17 vss n18 vss p18 vcc n19 vcc p19 vss n20 vss p20 vcc n21 vcc p21 vss n22 vss p22 vcc n23 vcc p23 vss n24 vss p24 vcc n25 vss p25 vcc_pll n26 clk_rst_dis p26 clk_pll_byp n27 clk_ref_clk_l p27 vss n28 clk_ref_clk_h p28 vddq n29 vss p29 qdr3_q_h[17] n30 qdr3_q_h[16] p30 qdr3_d_h[6] n31 vddq p31 qdr3_d_h[3] n32 qdr3_d_h[8] p32 vss n33 qdr3_d_h[7] p33 qdr3_d_h[5] n34 vss p34 vddq n35 qdr3_cin_l[0] p35 qdr3_d_h[12] n36 qdr3_a_h[23] p36 vddq n37 vss p37 qdr3_a_h[20] table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 7 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description datasheet 55 r1 spi4_tdat[3] t1 spi4_tdat[11] r2 spi4_tdat_l[3] t2 spi4_tdat_l[11] r3 vss t3 spi4_tclk r4 vcc33_pci t4 spi4_tclk_l r5 vcc33_pci t5 spi4_tdat[2] r6 vss t6 spi4_tdat_l[2] r7 pci_intb_l t7 spi4_preemp r8 pci_frame_l t8 pci_rst_l r9 pci_ad[23] t9 pci_clk r10 pci_cbe_l[1] t10 pci_ad[18] r11 pci_ad[12] t11 pci_perr_l r12 pci_zq2 t12 pci_cbe_l[2] r13 vcc t13 vss r14 vss t14 vcc r15 vcc t15 vss r16 vss t16 vcc r17 vcc t17 vss r18 vss t18 vcc r19 vcc t19 vss r20 vss t20 vcc r21 vcc t21 vss r22 vss t22 vcc r23 vcc t23 vss r24 vss t24 vcc r25 pas3_vcca t25 vss r26 vcc33 t26 vss r27 qdr3_q_h[1] t27 qdr3_q_h[0] r28 qdr3_q_h[2] t28 vddq r29 vss t29 qdr3_d_h[1] r30 qdr3_d_h[15] t30 qdr3_d_h[16] r31 vddq t31 qdr3_a_h[14] r32 qdr3_d_h[14] t32 vss r33 qdr3_d_h[4] t33 qdr3_c_l[1] r34 vss t34 vddq r35 qdr3_d_h[13] t35 qdr3_c_l[0] r36 qdr3_a_h[22] t36 vddq r37 vss t37 qdr3_a_h[21] table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 8 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description 56 datasheet u1 vcc25v v1 n/c u2 vss v2 spi4_tdat[6] u3 vcc25v v3 spi4_tdat_l[6] u4 spi4_tdat[1] v4 spi4_tdat[10] u5 spi4_tdat_l[1] v5 spi4_tdat_l[10] u6 vss v6 spi4_tdat[5] u7 vcc25v v7 spi4_tdat_l[5] u8 vcc33_pci v8 spi4_tdat[7] u9 vss v9 spi4_tdat_l[7] u10 pci_req_l[0] v10 vss u11 pci_ad[27] v11 vcc25v u12 pci_ad[24] v12 vss u13 vcc v13 vss u14 vss v14 vcc u15 vcc v15 vss u16 vss v16 vcc u17 vcc v17 vss u18 vss v18 vcc u19 vcc v19 vss u20 vss v20 vcc u21 vcc v21 vss u22 vss v22 vcc u23 vcc v23 vss u24 vss v24 vcc u25 vcc v25 vss u26 qdr3_d_h[2] v26 vss u27 qdr3_d_h[0] v27 qdr3_a_h[19] u28 qdr3_d_h[17] v28 vddq u29 vss v29 qdr3_a_h[3] u30 qdr3_zq[0] v30 qdr3_a_h[11] u31 vddq v31 qdr3_a_h[9] u32 qdr3_zq[1] v32 vss u33 qdr3_c_h[1] v33 qdr3_bws_l[1] u34 vss v34 vddq u35 qdr3_c_h[0] v35 qdr3_a_h[10] u36 qdr3_a_h[0] v36 vss u37 qdr3_k_h[1] v37 n/c table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 9 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description datasheet 57 w1 n/c y1 n/c w2 spi4_tdat[15] y2 vss w3 spi4_tdat_l[15] y3 spi4_tdat[8] w4 vss y4 spi4_tdat_l[8] w5 vcc25v y5 spi4_tdat[13] w6 spi4_tdat[14] y6 spi4_tdat_l[13] w7 spi4_tdat_l[14] y7 spi4_tdat[4] w8 vss y8 spi4_tdat_l[4] w9 vcc25v y9 spi4_tdat[12] w10 vss y10 spi4_tdat_l[12] w11 spi4_tdat[9] y11 spi4_rclk_ref w12 spi4_tdat_l[9] y12 spi4_rclk_ref_l w13 vcc y13 vss w14 vss y14 vcc w15 vcc y15 vss w16 vss y16 vcc w17 vcc y17 vss w18 vss y18 vcc w19 vcc y19 vss w20 vss y20 vcc w21 vcc y21 vss w22 vss y22 vcc w23 vcc y23 vss w24 vss y24 vcc w25 vcc y25 vss w26 vss y26 vss w27 qdr3_a_h[13] y27 qdr3_a_h[18] w28 qdr3_a_h[8] y28 vddq w29 vss y29 qdr3_a_h[12] w30 qdr3_rps_l[1] y30 qdr3_a_h[16] w31 vddq y31 qdr3_rps_l[0] w32 qdr3_bws_l[0] y32 vss w33 qdr3_wps_l[0] y33 qdr3_wps_l[1] w34 vss y34 vddq w35 qdr3_a_h[6] y35 qdr3_a_h[17] w36 qdr3_k_h[0] y36 vddq w37 n/c y37 n/c table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 10 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description 58 datasheet aa1 spi4_tprot ab1 vss aa2 spi4_tprot_l ab2 vcc25v aa3 spi4_tctl ab3 spi4_tpar aa4 spi4_tctl_l ab4 spi4_tpar_l aa5 vss ab5 spi4_rdat_l[11] aa6 vcc25v ab6 spi4_rdat[11] aa7 spi4_tdat[0] ab7 spi4_rdat_l[13] aa8 spi4_tdat_l[0] ab8 spi4_rdat[13] aa9 vss ab9 spi4_rpar_l aa10 vcc25v ab10 spi4_rpar aa11 vcc25v ab11 spi4_rprot_l aa12 vss ab12 spi4_rprot aa13 vcc ab13 vcca_spi4 aa14 vss ab14 vcc aa15 vcc ab15 vss aa16 vss ab16 vcc aa17 vcc ab17 vss aa18 vss ab18 vcc aa19 vcc ab19 vss aa20 vss ab20 vcc aa21 vcc ab21 vss aa22 vss ab22 vcc aa23 vcc ab23 vss aa24 vss ab24 vcc aa25 vcc ab25 vss aa26 vddq ab26 vss aa27 qdr2_a_h[19] ab27 qdr2_a_h[18] aa28 qdr2_a_h[12] ab28 vddq aa29 vss ab29 qdr2_a_h[11] aa30 qdr3_a_h[7] ab30 qdr2_a_h[9] aa31 vddq ab31 qdr2_a_h[14] aa32 qdr3_a_h[5] ab32 vss aa33 qdr3_a_h[4] ab33 vddq aa34 vss ab34 qdr3_a_h[2] aa35 qdr3_a_h[15] ab35 vddq aa36 qdr3_k_l[1] ab36 qdr3_a_h[1] aa37 qdr3_k_l[0] ab37 vss table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 11 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description datasheet 59 ac1 spi4_rdat_l[15] ad1 spi4_rdat_l[7] ac2 spi4_rdat[15] ad2 spi4_rdat[7] ac3 vss ad3 spi4_rdat_l[14] ac4 vcc25v ad4 spi4_rdat[14] ac5 spi4_rclk_l ad5 spi4_rctl_l ac6 spi4_rclk ad6 spi4_rctl ac7 vss ad7 spi4_tclk_ref_l ac8 vcc25v ad8 spi4_tclk_ref ac9 spi4_zq1 ad9 spi4_rdat_l[12] ac10 spi4_zq2 ad10 spi4_rdat[12] ac11 vrefhi ad11 vcc25v ac12 vreflo ad12 vss ac13 vcca_fc ad13 vcc_fuse ac14 vss ad14 vcc_fuse ac15 vcc ad15 vss ac16 vss ad16 vcc ac17 vcc ad17 vss ac18 vss ad18 vcc ac19 vcc ad19 vss ac20 vss ad20 vcc ac21 vcc ad21 vss ac22 vss ad22 vcc ac23 vcc ad23 vss ac24 vss ad24 vcc ac25 vcc ad25 vss ac26 vss ad26 vss ac27 vss ad27 vss ac28 qdr2_a_h[3] ad28 vddq ac29 vss ad29 qdr2_rps_l[1] ac30 qdr2_a_h[21] ad30 qdr2_rps_l[0] ac31 vddq ad31 qdr2_bws_l[0] ac32 qdr2_a_h[22] ad32 vss ac33 qdr2_a_h[20] ad33 qdr2_wps_l[1] ac34 vddq ad34 vss ac35 qdr2_a_h[10] ad35 qdr2_a_h[8] ac36 vddq ad36 qdr2_a_h[13] ac37 qdr2_k_l[0] ad37 vss table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 12 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description 60 datasheet ae1 vss af1 spi4_rdat_l[5] ae2 vcc25v af2 spi4_rdat[5] ae3 spi4_rdat_l[2] af3 spi4_rdat_l[10] ae4 spi4_rdat[2] af4 spi4_rdat[10] ae5 vss af5 spi4_rdat_l[3] ae6 vcc25v af6 spi4_rdat[3] ae7 spi4_rdat_l[6] af7 spi4_rdat_l[8] ae8 spi4_rdat[6] af8 spi4_rdat[8] ae9 vss af9 fc_txcdat[1] ae10 vcc25v af10 fc_txcdat_l[1] ae11 fc_txcdat_l[0] af11 fc_txcsrb_l ae12 fc_txcdat[0] af12 fc_txcsrb ae13 vcc_fuse af13 vss ae14 vcc_fuse af14 vss ae15 pas0_vcca af15 vddq ae16 vss af16 vss ae17 vcc af17 vss ae18 vss af18 qdr0_a_h[12] ae19 vcc af19 qdr0_k_h[0] ae20 vss af20 vss ae21 vcc af21 qdr1_a_h[1] ae22 vss af22 qdr1_a_h[5] ae23 vcc af23 qdr1_a_h[23] ae24 pas1_vcca af24 qdr1_q_h[0] ae25 pas2_vcca af25 vss ae26 vss af26 vddq ae27 qdr2_d_h[6] af27 qdr2_q_h[8] ae28 qdr2_d_h[8] af28 vddq ae29 vss af29 qdr2_d_h[10] ae30 qdr2_a_h[23] af30 qdr2_zq[1] ae31 vddq af31 qdr2_a_h[0] ae32 qdr2_a_h[7] af32 vss ae33 qdr2_wps_l[0] af33 qdr2_bws_l[1] ae34 vddq af34 vss ae35 qdr2_a_h[16] af35 qdr2_a_h[15] ae36 vddq af36 qdr2_k_h[0] ae37 qdr2_k_l[1] af37 vss table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 13 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description datasheet 61 ag1 spi4_rdat_l[4] ah1 spi4_rdat_l[0] ag2 spi4_rdat[4] ah2 spi4_rdat[0] ag3 spi4_rdat_l[1] ah3 vss ag4 spi4_rdat[1] ah4 vcc25v ag5 spi4_rdat_l[9] ah5 vss ag6 spi4_rdat[9] ah6 vcc25v ag7 vss ah7 fc_txcclk ag8 vcc25v ah8 fc_txcclk_l ag9 fc_preemp ah9 fc_txcdat[3] ag10 fc_txcdat[2] ah10 vss ag11 fc_txcdat_l[2] ah11 vddq ag12 vss ah12 qdr0_q_h[7] ag13 vss ah13 vddq ag14 qdr0_q_h[8] ah14 qdr0_q_h[9] ag15 qdr0_d_h[8] ah15 vddq ag16 qdr0_d_h[6] ah16 vss ag17 vss ah17 vddq ag18 qdr0_a_h[11] ah18 qdr0_a_h[9] ag19 qdr0_a_h[3] ah19 qdr0_k_l[0] ag20 qdr1_a_h[4] ah20 vddq ag21 qdr1_bws_l[0] ah21 qdr1_a_h[17] ag22 vss ah22 vddq ag23 qdr1_d_h[2] ah23 qdr1_d_h[0] ag24 qdr1_q_h[2] ah24 vddq ag25 qdr1_q_h[1] ah25 qdr1_q_h[17] ag26 qdr1_q_h[16] ah26 vddq ag27 qdr2_q_h[7] ah27 qdr1_q_h[15] ag28 qdr2_q_h[9] ah28 vddq ag29 vss ah29 qdr2_q_h[6] ag30 qdr2_d_h[9] ah30 qdr2_d_h[7] ag31 vddq ah31 qdr2_d_h[11] ag32 qdr2_zq[0] ah32 vss ag33 qdr2_a_h[1] ah33 qdr2_a_h[2] ag34 vddq ah34 vss ag35 qdr2_a_h[6] ah35 qdr2_c_h[0] ag36 vddq ah36 qdr2_a_h[17] ag37 qdr2_k_h[1] ah37 vss table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 14 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description 62 datasheet aj1 vss ak1 fc_rxcfc aj2 vcc25v ak2 fc_rxcfc_l aj3 fc_txcfc ak3 fc_rxcpar aj4 fc_txcfc_l ak4 fc_rxcpar_l aj5 fc_txcsof ak5 fc_rxcdat[3] aj6 fc_txcsof_l ak6 fc_rxcdat_l[3] aj7 fc_txcpar ak7 fc_zq2 aj8 fc_txcpar_l ak8 vddq aj9 fc_txcdat_l[3] ak9 vss aj10 vss ak10 qdr0_q_h[10] aj11 qdr0_q_h[6] ak11 qdr0_d_h[2] aj12 vss ak12 qdr0_d_h[12] aj13 qdr0_d_h[10] ak13 qdr0_zq[0] aj14 vss ak14 qdr0_d_h[9] aj15 vss ak15 qdr0_rps_l[0] aj16 vss ak16 qdr0_a_h[23] aj17 qdr0_a_h[14] ak17 qdr0_a_h[22] aj18 vss ak18 qdr0_a_h[19] aj19 vss ak19 qdr1_a_h[22] aj20 qdr1_a_h[3] ak20 qdr1_a_h[12] aj21 vss ak21 qdr1_a_h[21] aj22 qdr1_d_h[17] ak22 qdr1_rps_l[0] aj23 vss ak23 qdr1_d_h[1] aj24 qdr1_d_h[6] ak24 qdr1_d_h[16] aj25 vss ak25 qdr1_d_h[10] aj26 qdr1_q_h[3] ak26 qdr1_d_h[8] aj27 vss ak27 qdr1_q_h[14] aj28 qdr1_q_h[8] ak28 qdr1_q_h[7] aj29 vss ak29 qdr2_q_h[10] aj30 qdr2_d_h[5] ak30 qdr2_q_h[11] aj31 vddq ak31 qdr2_d_h[2] aj32 qdr2_d_h[13] ak32 vss aj33 qdr2_d_h[12] ak33 qdr2_d_h[3] aj34 vddq ak34 vss aj35 qdr2_c_l[0] ak35 qdr2_d_h[4] aj36 vddq ak36 qdr2_a_h[4] aj37 qdr2_c_h[1] ak37 vss table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 15 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description datasheet 63 al1 fc_rxcsof am1 fc_rxcclk al2 fc_rxcsof_l am2 fc_rxcclk_l al3 vss am3 fc_rxcdat[2] al4 vcc25v am4 fc_rxcdat_l[2] al5 vrefhi am5 vss al6 vreflo am6 qdr0_q_h[0] al7 fc_zq1 am7 qdr0_q_h[5] al8 qdr0_q_h[11] am8 qdr0_q_h[13] al9 qdr0_q_h[12] am9 vss al10 vddq am10 qdr0_d_h[17] al11 qdr0_d_h[0] am11 vss al12 vddq am12 qdr0_zq[1] al13 qdr0_d_h[11] am13 vss al14 vddq am14 qdr0_d_h[7] al15 qdr0_rps_l[1] am15 vss al16 vddq am16 vss al17 qdr0_a_h[20] am17 vss al18 qdr0_a_h[0] am18 qdr0_a_h[7] al19 vddq am19 qdr1_a_h[20] al20 qdr1_a_h[11] am20 vss al21 vddq am21 qdr1_a_h[9] al22 qdr1_rps_l[1] am22 vss al23 vddq am23 qdr1_zq[0] al24 qdr1_zq[1] am24 vss al25 vddq am25 qdr1_d_h[3] al26 qdr1_d_h[9] am26 vss al27 vddq am27 qdr1_d_h[7] al28 qdr1_q_h[4] am28 vss al29 vddq am29 qdr1_q_h[13] al30 qdr2_q_h[12] am30 vss al31 qdr2_q_h[5] am31 qdr2_q_h[13] al32 qdr2_d_h[16] am32 vss al33 qdr2_d_h[0] am33 qdr2_cin_h[0] al34 vddq am34 vss al35 qdr2_d_h[14] am35 qdr2_cin_l[0] al36 vddq am36 qdr2_a_h[5] al37 qdr2_c_l[1] am37 vss table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 16 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description 64 datasheet an1 vcc25v ap1 fc_rxcsrb an2 vss ap2 fc_rxcsrb_l an3 fc_rxcdat[1] ap3 fc_rxcdat[0] an4 fc_rxcdat[1]_l ap4 fc_rxcdat[0]_l an5 vcc25v ap5 vddq an6 qdr0_q_h[1] ap6 vss an7 qdr0_q_h[4] ap7 qdr0_q_h[17] an8 qdr0_cin_h[1] ap8 vss an9 qdr0_cin_h[0] ap9 vddq an10 qdr0_d_h[15] ap10 vss an11 qdr0_d_h[14] ap11 vddq an12 qdr0_d_h[5] ap12 vss an13 qdr0_a_h[18] ap13 vddq an14 qdr0_a_h[17] ap14 vss an15 qdr0_wps_l[0] ap15 vddq an16 qdr0_bws_l[1] ap16 vss an17 qdr0_a_h[8] ap17 vddq an18 qdr0_wps_l[1] ap18 vss an19 qdr1_a_h[19] ap19 qdr1_k_h[0] an20 qdr1_wps_l[1] ap20 vss an21 qdr1_wps_l[0] ap21 vddq an22 qdr1_bws_l[1] ap22 vss an23 qdr1_a_h[0] ap23 vddq an24 qdr1_a_h[14] ap24 vss an25 qdr1_d_h[15] ap25 vddq an26 qdr1_d_h[5] ap26 vss an27 qdr1_d_h[11] ap27 vddq an28 qdr1_cin_h[0] ap28 vss an29 qdr1_cin_h[1] ap29 vddq an30 qdr1_q_h[9] ap30 vss an31 qdr2_q_h[15] ap31 vddq an32 qdr2_q_h[4] ap32 vss an33 qdr2_cin_h[1] ap33 vddq an34 vddq ap34 vss an35 qdr2_cin_l[1] ap35 qdr2_q_h[14] an36 vddq ap36 qdr2_d_h[1] an37 qdr2_d_h[15] ap37 vss table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 17 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description datasheet 65 ar1 vss at1 vddq ar2 vddq at2 vref_qdr0 ar3 vss at3 qdr0_q_h[2] ar4 vddq at4 qdr0_q_h[16] ar5 qdr0_q_h[3] at5 vddq ar6 qdr0_q_h[15] at6 qdr0_d_h[16] ar7 qdr0_q_h[14] at7 vddq ar8 qdr0_cin_l[1] at8 qdr0_a_h[1] ar9 qdr0_cin_l[0] at9 vddq ar10 qdr0_d_h[4] at10 qdr0_a_h[2] ar11 qdr0_d_h[13] at11 vddq ar12 qdr0_c_l[0] at12 qdr0_a_h[5] ar13 qdr0_c_h[0] at13 vddq ar14 qdr0_bws_l[0] at14 qdr0_k_l[1] ar15 qdr0_a_h[21] at15 vddq ar16 qdr0_a_h[6] at16 qdr0_a_h[16] ar17 qdr0_k_h[1] at17 vddq ar18 qdr0_a_h[10] at18 qdr1_a_h[2] ar19 qdr1_k_l[0] at19 vddq ar20 qdr1_a_h[6] at20 qdr1_a_h[18] ar21 qdr1_a_h[15] at21 vddq ar22 qdr1_a_h[13] at22 qdr1_k_l[1] ar23 qdr1_k_h[1] at23 vddq ar24 qdr1_a_h[10] at24 qdr1_c_h[0] ar25 qdr1_a_h[7] at25 vddq ar26 qdr1_d_h[14] at26 qdr1_c_l[0] ar27 qdr1_d_h[4] at27 vddq ar28 qdr1_cin_l[0] at28 qdr1_d_h[13] ar29 qdr1_cin_l[1] at29 vddq ar30 qdr1_q_h[11] at30 qdr1_q_h[5] ar31 qdr1_q_h[6] at31 vddq ar32 qdr1_q_h[10] at32 vref_qdr1 ar33 qdr2_q_h[0] at33 vddq ar34 qdr2_q_h[1] at34 qdr2_q_h[17] ar35 qdr2_q_h[3] at35 vddq ar36 vddq at36 qdr2_q_h[16] ar37 qdr2_d_h[17] at37 vref_qdr2 table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 18 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description 66 datasheet au1 vss au19 n/c au2 vss au20 n/c au3 vref_qdr0 au21 qdr1_a_h[16] au4 vss au22 vss au5 qdr0_d_h[1] au23 qdr1_a_h[8] au6 vss au24 vss au7 qdr0_d_h[3] au25 qdr1_c_h[1] au8 vss au26 vss au9 qdr0_c_l[1] au27 qdr1_c_l[1] au10 vss au28 vss au11 qdr0_c_h[1] au29 qdr1_d_h[12] au12 vss au30 vss au13 qdr0_a_h[4] au31 qdr1_q_h[12] au14 vss au32 vss au15 qdr0_a_h[15] au33 vref_qdr1 au16 vss au34 vss au17 qdr0_a_h[13] au35 qdr2_q_h[2] au18 n/c au36 vref_qdr2 au37 vss table 18. ixp2800/ixp2850 network processor fcbga location pin list (sheet 19 of 19) fcbga location pin name fcbga location pin name
intel ? ixp2800 and ixp2850 network processors signal description datasheet 67 3.2.13.2 pins listed in alphabetic order table 19 lists the network processor pins in alphabetic order, showing the name and location code of each pin. table 19. ixp2800/ixp2850 network processo r alphabetical pin list (sheet 1 of 20) pin name fcbga location pin name fcbga location clk_cfg_rst_dir k23 fc_txcdat_l[0] ae11 clk_nreset l20 fc_txcdat_l[1] af10 clk_nreset_out l21 fc_txcdat_l[2] ag11 clk_phase_ref m29 fc_txcdat_l[3] aj9 clk_pll_byp p26 fc_txcfc aj3 clk_ref_clk_h n28 fc_txcfc_l aj4 clk_ref_clk_l n27 fc_txcpar aj7 clk_rst_dis n26 fc_txcpar_l aj8 clk_stop k22 fc_txcsof aj5 fc_preemp ag9 fc_txcsof_l aj6 fc_rxcclk am1 fc_txcsrb af12 fc_rxcclk_l am2 fc_txcsrb_l af11 fc_rxcdat[0] ap3 fc_zq1 al7 fc_rxcdat[0]_l ap4 fc_zq2 ak7 fc_rxcdat[1] an3 gpio[0] k25 fc_rxcdat[1]_l an4 gpio[1] h27 fc_rxcdat[2] am3 gpio[2] j26 fc_rxcdat[2]_l am4 gpio[3] j21 fc_rxcdat[3] ak5 gpio[4] j27 fc_rxcdat_l[3] ak6 gpio[5] k24 fc_rxcfc ak1 gpio[6] l24 fc_rxcfc_l ak2 gpio[7] h21 fc_rxcpar ak3 jtag_tck m20 fc_rxcpar_l ak4 jtag_tdi j23 fc_rxcsof al1 jtag_tdo m25 fc_rxcsof_l al2 jtag_tms j22 fc_rxcsrb ap1 jtag_trst k21 fc_rxcsrb_l ap2 n/c a1 fc_txcclk ah7 n/c a18 fc_txcclk_l ah8 n/c a19 fc_txcdat[0] ae12 n/c a20 fc_txcdat[1] af9 n/c au18 fc_txcdat[2] ag10 n/c au19 fc_txcdat[3] ah9 n/c au20
intel ? ixp2800 and ixp2850 network processors signal description 68 datasheet n/c v1 pci_ad[18] t10 n/c v37 pci_ad[19] n7 n/c w1 pci_ad[20] k3 n/c w37 pci_ad[21] l6 n/c y1 pci_ad[22] m4 n/c y37 pci_ad[23] r9 par0_padvrefa f9 pci_ad[24] u12 par0_padvrefb f6 pci_ad[25] k12 par1_padvrefa f20 pci_ad[26] p6 par1_padvrefb f18 pci_ad[27] u11 par2_padvrefa f34 pci_ad[28] l2 par2_padvrefb f31 pci_ad[29] j1 pas0_vcca ae15 pci_ad[30] m6 pas1_vcca ae24 pci_ad[31] m5 pas2_vcca ae25 pci_ad[32] k11 pas3_vcca r25 pci_ad[33] h9 pci_ack64_l j14 pci_ad[34] j11 pci_ad[0] l9 pci_ad[35] h8 pci_ad[1] k6 pci_ad[36] k18 pci_ad[2] j12 pci_ad[37] m12 pci_ad[3] m9 pci_ad[38] h6 pci_ad[4] n9 pci_ad[39] j16 pci_ad[5] k5 pci_ad[40] j10 pci_ad[6] p10 pci_ad[41] j18 pci_ad[7] m8 pci_ad[42] h5 pci_ad[8] j4 pci_ad[43] l17 pci_ad[9] h3 pci_ad[44] j9 pci_ad[10] j3 pci_ad[45] k10 pci_ad[11] k13 pci_ad[46] m11 pci_ad[12] r11 pci_ad[47] h15 pci_ad[13] k4 pci_ad[48] j8 pci_ad[14] m14 pci_ad[49] k16 pci_ad[15] h2 pci_ad[50] l18 pci_ad[16] m7 pci_ad[51] k14 pci_ad[17] l4 pci_ad[52] n12 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 2 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description datasheet 69 pci_ad[53] h11 pci_rst_l t8 pci_ad[54] k9 pci_serr_l p8 pci_ad[55] j7 pci_stop_l l15 pci_ad[56] j6 pci_trdy_l l7 pci_ad[57] k15 pci_zq1 n8 pci_ad[58] n11 pci_zq2 r12 pci_ad[59] h12 qdr0_a_h[0] al18 pci_ad[60] l10 qdr0_a_h[1] at8 pci_ad[61] j5 qdr0_a_h[2] at10 pci_ad[62] m10 qdr0_a_h[3] ag19 pci_ad[63] l16 qdr0_a_h[4] au13 pci_cbe_l[0] l13 qdr0_a_h[5] at12 pci_cbe_l[1] r10 qdr0_a_h[6] ar16 pci_cbe_l[2] t12 qdr0_a_h[7] am18 pci_cbe_l[3] n4 qdr0_a_h[8] an17 pci_cbe_l[4] j15 qdr0_a_h[9] ah18 pci_cbe_l[5] n10 qdr0_a_h[10] ar18 pci_cbe_l[6] m15 qdr0_a_h[11] ag18 pci_cbe_l[7] k7 qdr0_a_h[12] af18 pci_clk t9 qdr0_a_h[13] au17 pci_devsel_l n5 qdr0_a_h[14] aj17 pci_frame_l r8 qdr0_a_h[15] au15 pci_gnt_l[0] k1 qdr0_a_h[16] at16 pci_gnt_l[1] l1 qdr0_a_h[17] an14 pci_idsel m3 qdr0_a_h[18] an13 pci_inta_l m2 qdr0_a_h[19] ak18 pci_intb_l r7 qdr0_a_h[20] al17 pci_irdy_l p7 qdr0_a_h[21] ar15 pci_m66en l12 qdr0_a_h[22] ak17 pci_par j2 qdr0_a_h[23] ak16 pci_par64 k8 qdr0_bws_l[0] ar14 pci_perr_l t11 qdr0_bws_l[1] an16 pci_req_l[0] u10 qdr0_c_h[0] ar13 pci_req_l[1] n6 qdr0_c_h[1] au11 pci_req64_l p12 qdr0_c_l[0] ar12 table 19. ixp2800/ixp2850 network processo r alphabetical pin list (sheet 3 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description 70 datasheet qdr0_c_l[1] au9 qdr0_q_h[8] ag14 qdr0_cin_h[0] an9 qdr0_q_h[9] ah14 qdr0_cin_h[1] an8 qdr0_q_h[10] ak10 qdr0_cin_l[0] ar9 qdr0_q_h[11] al8 qdr0_cin_l[1] ar8 qdr0_q_h[12] al9 qdr0_d_h[0] al11 qdr0_q_h[13] am8 qdr0_d_h[1] au5 qdr0_q_h[14] ar7 qdr0_d_h[2] ak11 qdr0_q_h[15] ar6 qdr0_d_h[3] au7 qdr0_q_h[16] at4 qdr0_d_h[4] ar10 qdr0_q_h[17] ap7 qdr0_d_h[5] an12 qdr0_rps_l[0] ak15 qdr0_d_h[6] ag16 qdr0_rps_l[1] al15 qdr0_d_h[7] am14 qdr0_wps_l[0] an15 qdr0_d_h[8] ag15 qdr0_wps_l[1] an18 qdr0_d_h[9] ak14 qdr0_zq[0] ak13 qdr0_d_h[10] aj13 qdr0_zq[1] am12 qdr0_d_h[11] al13 qdr1_a_h[0] an23 qdr0_d_h[12] ak12 qdr1_a_h[1] af21 qdr0_d_h[13] ar11 qdr1_a_h[2] at18 qdr0_d_h[14] an11 qdr1_a_h[3] aj20 qdr0_d_h[15] an10 qdr1_a_h[4] ag20 qdr0_d_h[16] at6 qdr1_a_h[5] af22 qdr0_d_h[17] am10 qdr1_a_h[6] ar20 qdr0_k_h[0] af19 qdr1_a_h[7] ar25 qdr0_k_h[1] ar17 qdr1_a_h[8] au23 qdr0_k_l[0] ah19 qdr1_a_h[9] am21 qdr0_k_l[1] at14 qdr1_a_h[10] ar24 qdr0_q_h[0] am6 qdr1_a_h[11] al20 qdr0_q_h[1] an6 qdr1_a_h[12] ak20 qdr0_q_h[2] at3 qdr1_a_h[13] ar22 qdr0_q_h[3] ar5 qdr1_a_h[14] an24 qdr0_q_h[4] an7 qdr1_a_h[15] ar21 qdr0_q_h[5] am7 qdr1_a_h[16] au21 qdr0_q_h[6] aj11 qdr1_a_h[17] ah21 qdr0_q_h[7] ah12 qdr1_a_h[18] at20 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 4 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description datasheet 71 qdr1_a_h[19] an19 qdr1_k_l[0] ar19 qdr1_a_h[20] am19 qdr1_k_l[1] at22 qdr1_a_h[21] ak21 qdr1_q_h[0] af24 qdr1_a_h[22] ak19 qdr1_q_h[1] ag25 qdr1_a_h[23] af23 qdr1_q_h[2] ag24 qdr1_bws_l[0] ag21 qdr1_q_h[3] aj26 qdr1_bws_l[1] an22 qdr1_q_h[4] al28 qdr1_c_h[0] at24 qdr1_q_h[5] at30 qdr1_c_h[1] au25 qdr1_q_h[6] ar31 qdr1_c_l[0] at26 qdr1_q_h[7] ak28 qdr1_c_l[1] au27 qdr1_q_h[8] aj28 qdr1_cin_h[0] an28 qdr1_q_h[9] an30 qdr1_cin_h[1] an29 qdr1_q_h[10] ar32 qdr1_cin_l[0] ar28 qdr1_q_h[11] ar30 qdr1_cin_l[1] ar29 qdr1_q_h[12] au31 qdr1_d_h[0] ah23 qdr1_q_h[13] am29 qdr1_d_h[1] ak23 qdr1_q_h[14] ak27 qdr1_d_h[2] ag23 qdr1_q_h[15] ah27 qdr1_d_h[3] am25 qdr1_q_h[16] ag26 qdr1_d_h[4] ar27 qdr1_q_h[17] ah25 qdr1_d_h[5] an26 qdr1_rps_l[0] ak22 qdr1_d_h[6] aj24 qdr1_rps_l[1] al22 qdr1_d_h[7] am27 qdr1_wps_l[0] an21 qdr1_d_h[8] ak26 qdr1_wps_l[1] an20 qdr1_d_h[9] al26 qdr1_zq[0] am23 qdr1_d_h[10] ak25 qdr1_zq[1] al24 qdr1_d_h[11] an27 qdr2_a_h[0] af31 qdr1_d_h[12] au29 qdr2_a_h[1] ag33 qdr1_d_h[13] at28 qdr2_a_h[2] ah33 qdr1_d_h[14] ar26 qdr2_a_h[3] ac28 qdr1_d_h[15] an25 qdr2_a_h[4] ak36 qdr1_d_h[16] ak24 qdr2_a_h[5] am36 qdr1_d_h[17] aj22 qdr2_a_h[6] ag35 qdr1_k_h[0] ap19 qdr2_a_h[7] ae32 qdr1_k_h[1] ar23 qdr2_a_h[8] ad35 table 19. ixp2800/ixp2850 network processo r alphabetical pin list (sheet 5 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description 72 datasheet qdr2_a_h[9] ab30 qdr2_d_h[10] af29 qdr2_a_h[10] ac35 qdr2_d_h[11] ah31 qdr2_a_h[11] ab29 qdr2_d_h[12] aj33 qdr2_a_h[12] aa28 qdr2_d_h[13] aj32 qdr2_a_h[13] ad36 qdr2_d_h[14] al35 qdr2_a_h[14] ab31 qdr2_d_h[15] an37 qdr2_a_h[15] af35 qdr2_d_h[16] al32 qdr2_a_h[16] ae35 qdr2_d_h[17] ar37 qdr2_a_h[17] ah36 qdr2_k_h[0] af36 qdr2_a_h[18] ab27 qdr2_k_h[1] ag37 qdr2_a_h[19] aa27 qdr2_k_l[0] ac37 qdr2_a_h[20] ac33 qdr2_k_l[1] ae37 qdr2_a_h[21] ac30 qdr2_q_h[0] ar33 qdr2_a_h[22] ac32 qdr2_q_h[1] ar34 qdr2_a_h[23] ae30 qdr2_q_h[2] au35 qdr2_bws_l[0] ad31 qdr2_q_h[3] ar35 qdr2_bws_l[1] af33 qdr2_q_h[4] an32 qdr2_c_h[0] ah35 qdr2_q_h[5] al31 qdr2_c_h[1] aj37 qdr2_q_h[6] ah29 qdr2_c_l[0] aj35 qdr2_q_h[7] ag27 qdr2_c_l[1] al37 qdr2_q_h[8] af27 qdr2_cin_h[0] am33 qdr2_q_h[9] ag28 qdr2_cin_h[1] an33 qdr2_q_h[10] ak29 qdr2_cin_l[0] am35 qdr2_q_h[11] ak30 qdr2_cin_l[1] an35 qdr2_q_h[12] al30 qdr2_d_h[0] al33 qdr2_q_h[13] am31 qdr2_d_h[1] ap36 qdr2_q_h[14] ap35 qdr2_d_h[2] ak31 qdr2_q_h[15] an31 qdr2_d_h[3] ak33 qdr2_q_h[16] at36 qdr2_d_h[4] ak35 qdr2_q_h[17] at34 qdr2_d_h[5] aj30 qdr2_rps_l[0] ad30 qdr2_d_h[6] ae27 qdr2_rps_l[1] ad29 qdr2_d_h[7] ah30 qdr2_wps_l[0] ae33 qdr2_d_h[8] ae28 qdr2_wps_l[1] ad33 qdr2_d_h[9] ag30 qdr2_zq[0] ag32 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 6 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description datasheet 73 qdr2_zq[1] af30 qdr3_d_h[0] u27 qdr3_a_h[0] u36 qdr3_d_h[1] t29 qdr3_a_h[1] ab36 qdr3_d_h[2] u26 qdr3_a_h[2] ab34 qdr3_d_h[3] p31 qdr3_a_h[3] v29 qdr3_d_h[4] r33 qdr3_a_h[4] aa33 qdr3_d_h[5] p33 qdr3_a_h[5] aa32 qdr3_d_h[6] p30 qdr3_a_h[6] w35 qdr3_d_h[7] n33 qdr3_a_h[7] aa30 qdr3_d_h[8] n32 qdr3_a_h[8] w28 qdr3_d_h[9] k37 qdr3_a_h[9] v31 qdr3_d_h[10] l36 qdr3_a_h[10] v35 qdr3_d_h[11] m37 qdr3_a_h[11] v30 qdr3_d_h[12] p35 qdr3_a_h[12] y29 qdr3_d_h[13] r35 qdr3_a_h[13] w27 qdr3_d_h[14] r32 qdr3_a_h[14] t31 qdr3_d_h[15] r30 qdr3_a_h[15] aa35 qdr3_d_h[16] t30 qdr3_a_h[16] y30 qdr3_d_h[17] u28 qdr3_a_h[17] y35 qdr3_k_h[0] w36 qdr3_a_h[18] y27 qdr3_k_h[1] u37 qdr3_a_h[19] v27 qdr3_k_l[0] aa37 qdr3_a_h[20] p37 qdr3_k_l[1] aa36 qdr3_a_h[21] t37 qdr3_q_h[0] t27 qdr3_a_h[22] r36 qdr3_q_h[1] r27 qdr3_a_h[23] n36 qdr3_q_h[2] r28 qdr3_bws_l[0] w32 qdr3_q_h[3] m30 qdr3_bws_l[1] v33 qdr3_q_h[4] k35 qdr3_c_h[0] u35 qdr3_q_h[5] j35 qdr3_c_h[1] u33 qdr3_q_h[6] j32 qdr3_c_l[0] t35 qdr3_q_h[7] k31 qdr3_c_l[1] t33 qdr3_q_h[8] l30 qdr3_cin_h[0] m33 qdr3_q_h[9] h32 qdr3_cin_h[1] l33 qdr3_q_h[10] h33 qdr3_cin_l[0] n35 qdr3_q_h[11] j33 qdr3_cin_l[1] m35 qdr3_q_h[12] k33 table 19. ixp2800/ixp2850 network processo r alphabetical pin list (sheet 7 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description 74 datasheet qdr3_q_h[13] j36 rdr0_rq[0] a5 qdr3_q_h[14] l32 rdr0_rq[1] e6 qdr3_q_h[15] m31 rdr0_rq[2] c6 qdr3_q_h[16] n30 rdr0_rq[3] a6 qdr3_q_h[17] p29 rdr0_rq[4] e7 qdr3_rps_l[0] y31 rdr0_rq[5] c7 qdr3_rps_l[1] w30 rdr0_rq[6] a7 qdr3_wps_l[0] w33 rdr0_rq[7] e8 qdr3_wps_l[1] y33 rdr0_sck f1 qdr3_zq[0] u30 rdr0_sclkn f2 qdr3_zq[1] u32 rdr0_sio d1 rdr0_cfm c9 rdr1_cfm c22 rdr0_cfmn c8 rdr1_cfmn c21 rdr0_cmd b1 rdr1_cmd a13 rdr0_ctm a9 rdr1_ctm a22 rdr0_ctmn a8 rdr1_ctmn a21 rdr0_dqa[0] e10 rdr1_dqa[0] a23 rdr0_dqa[1] c10 rdr1_dqa[1] c23 rdr0_dqa[2] a10 rdr1_dqa[2] a24 rdr0_dqa[3] e11 rdr1_dqa[3] e23 rdr0_dqa[4] c11 rdr1_dqa[4] c24 rdr0_dqa[5] a11 rdr1_dqa[5] e24 rdr0_dqa[6] a12 rdr1_dqa[6] a25 rdr0_dqa[7] c12 rdr1_dqa[7] e25 rdr0_dqa[8] e12 rdr1_dqa[8] c25 rdr0_dqb[0] e5 rdr1_dqb[0] e17 rdr0_dqb[1] c5 rdr1_dqb[1] c17 rdr0_dqb[2] a4 rdr1_dqb[2] c16 rdr0_dqb[3] c4 rdr1_dqb[3] e16 rdr0_dqb[4] e4 rdr1_dqb[4] a16 rdr0_dqb[5] a3 rdr1_dqb[5] c15 rdr0_dqb[6] c3 rdr1_dqb[6] e15 rdr0_dqb[7] e3 rdr1_dqb[7] a15 rdr0_dqb[8] a2 rdr1_dqb[8] a14 rdr0_pclkm d2 rdr1_pclkm d14 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 8 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description datasheet 75 rdr1_rq[0] a17 rdr2_rq[0] a30 rdr1_rq[1] b18 rdr2_rq[1] a31 rdr1_rq[2] d18 rdr2_rq[2] c31 rdr1_rq[3] c19 rdr2_rq[3] e31 rdr1_rq[4] e19 rdr2_rq[4] a32 rdr1_rq[5] b20 rdr2_rq[5] c32 rdr1_rq[6] e21 rdr2_rq[6] e32 rdr1_rq[7] d20 rdr2_rq[7] e33 rdr1_sck d13 rdr2_sck c26 rdr1_sclkn b13 rdr2_sclkn d26 rdr1_sio f14 rdr2_sio a26 rdr2_cfm c34 sp_ack_l j25 rdr2_cfmn c33 sp_ad[0] h19 rdr2_cmd e26 sp_ad[1] h25 rdr2_ctm a34 sp_ad[2] k27 rdr2_ctmn a33 sp_ad[3] l27 rdr2_dqa[0] a35 sp_ad[4] k20 rdr2_dqa[1] c35 sp_ad[5] h28 rdr2_dqa[2] e35 sp_ad[6] j28 rdr2_dqa[3] a36 sp_ad[7] j24 rdr2_dqa[4] c36 sp_ale_l l25 rdr2_dqa[5] e36 sp_clk m26 rdr2_dqa[6] d37 sp_cp m23 rdr2_dqa[7] f37 sp_cs_l[0] m24 rdr2_dqa[8] b37 sp_cs_l[1] j20 rdr2_dqb[0] e29 sp_dir k28 rdr2_dqb[1] c30 sp_oe_l m27 rdr2_dqb[2] e30 sp_rd_l h24 rdr2_dqb[3] c29 sp_wr_l l26 rdr2_dqb[4] a29 spi4_preemp t7 rdr2_dqb[5] e28 spi4_rclk ac6 rdr2_dqb[6] c28 spi4_rclk_l ac5 rdr2_dqb[7] a28 spi4_rclk_ref y11 rdr2_dqb[8] a27 spi4_rclk_ref_l y12 rdr2_pclkm d27 spi4_rctl ad6 table 19. ixp2800/ixp2850 network processo r alphabetical pin list (sheet 9 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description 76 datasheet spi4_rctl_l ad5 spi4_rprot ab12 spi4_rdat[0] ah2 spi4_rprot_l ab11 spi4_rdat[1] ag4 spi4_rsclk n2 spi4_rdat[2] ae4 spi4_rstat[0] n1 spi4_rdat[3] af6 spi4_rstat[1] n3 spi4_rdat[4] ag2 spi4_tclk t3 spi4_rdat[5] af2 spi4_tclk_l t4 spi4_rdat[6] ae8 spi4_tclk_ref ad8 spi4_rdat[7] ad2 spi4_tclk_ref_l ad7 spi4_rdat[8] af8 spi4_tctl aa3 spi4_rdat[9] ag6 spi4_tctl_l aa4 spi4_rdat[10] af4 spi4_tdat[0] aa7 spi4_rdat[11] ab6 spi4_tdat[1] u4 spi4_rdat[12] ad10 spi4_tdat[2] t5 spi4_rdat[13] ab8 spi4_tdat[3] r1 spi4_rdat[14] ad4 spi4_tdat[4] y7 spi4_rdat[15] ac2 spi4_tdat[5] v6 spi4_rdat_l[0] ah1 spi4_tdat[6] v2 spi4_rdat_l[1] ag3 spi4_tdat[7] v8 spi4_rdat_l[2] ae3 spi4_tdat[8] y3 spi4_rdat_l[3] af5 spi4_tdat[9] w11 spi4_rdat_l[4] ag1 spi4_tdat[10] v4 spi4_rdat_l[5] af1 spi4_tdat[11] t1 spi4_rdat_l[6] ae7 spi4_tdat[12] y9 spi4_rdat_l[7] ad1 spi4_tdat[13] y5 spi4_rdat_l[8] af7 spi4_tdat[14] w6 spi4_rdat_l[9] ag5 spi4_tdat[15] w2 spi4_rdat_l[10] af3 spi4_tdat_l[0] aa8 spi4_rdat_l[11] ab5 spi4_tdat_l[1] u5 spi4_rdat_l[12] ad9 spi4_tdat_l[2] t6 spi4_rdat_l[13] ab7 spi4_tdat_l[3] r2 spi4_rdat_l[14] ad3 spi4_tdat_l[4] y8 spi4_rdat_l[15] ac1 spi4_tdat_l[5] v7 spi4_rpar ab10 spi4_tdat_l[6] v3 spi4_rpar_l ab9 spi4_tdat_l[7] v9 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 10 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description datasheet 77 spi4_tdat_l[8] y4 vcc ab18 spi4_tdat_l[9] w12 vcc ab20 spi4_tdat_l[10] v5 vcc ac21 spi4_tdat_l[11] t2 vcc ac23 spi4_tdat_l[12] y10 vcc ac25 spi4_tdat_l[13] y6 vcc ad16 spi4_tdat_l[14] w7 vcc ad18 spi4_tdat_l[15] w3 vcc ad20 spi4_tpar ab3 vcc ad22 spi4_tpar_l ab4 vcc ad24 spi4_tprot aa1 vcc ae17 spi4_tprot_l aa2 vcc ae19 spi4_tsclk p4 vcc ae21 spi4_tstat[0] p5 vcc ae23 spi4_tstat[1] p3 vcc n13 spi4_zq1 ac9 vcc n15 spi4_zq2 ac10 vcc n17 sr_rx h22 vcc n19 sr_tx k26 vcc n21 test_scan_mode m21 vcc n23 test_diode_a j29 vcc p14 test_diode_c k29 vcc p16 interrupt_mode m22 vcc p18 test_scan_clk_a l28 vcc p20 test_scan_clk_b m28 vcc p22 test_scan_en h20 vcc p24 vcc aa13 vcc r13 vcc aa15 vcc r15 vcc aa17 vcc r17 vcc aa19 vcc r19 vcc aa21 vcc r21 vcc aa23 vcc r23 vcc aa25 vcc t14 vcc ab14 vcc t16 vcc ab16 vcc t18 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 11 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description 78 datasheet vcc ab22 vcc_fuse ad13 vcc ab24 vcc_fuse ad14 vcc ac15 vcc_fuse ae13 vcc ac17 vcc_fuse ae14 vcc ac19 vcc_pll p25 vcc u17 vcc25v ae2 vcc u19 vcc25v ae6 vcc u21 vcc25v ag8 vcc u23 vcc25v ah4 vcc u25 vcc25v ah6 vcc v14 vcc25v aj2 vcc v16 vcc25v al4 vcc v18 vcc25v an1 vcc v20 vcc25v an5 vcc v22 vcc25v j13 vcc v24 vcc25v j17 vcc w13 vcc25v m13 vcc w15 vcc25v m18 vcc w17 vcc25v p1 vcc w19 vcc25v u1 vcc w21 vcc25v u3 vcc w23 vcc25v u7 vcc w25 vcc25v v11 vcc y14 vcc25v w5 vcc y16 vcc25v w9 vcc y18 vcc25v aa10 vcc y20 vcc25v aa11 vcc y22 vcc25v aa6 vcc y24 vcc25v ab2 vcc t20 vcc25v ac4 vcc t22 vcc25v ac8 vcc t24 vcc25v ad11 vcc u13 vcc25v ae10 vcc u15 vcc33 h26 vcc_clk j19 vcc33 l22 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 12 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description datasheet 79 vcc33 l29 vccra g9 vcc33 r26 vccrio g1 vcc33_pci h1 vccrio g11 vcc33_pci h13 vccrio g15 vcc33_pci h16 vccrio g17 vcc33_pci h7 vccrio g24 vcc33_pci l14 vccrio g26 vcc33_pci l3 vccrio g28 vcc33_pci l8 vccrio g3 vcc33_pci m17 vccrio g36 vcc33_pci p11 vddq ae31 vcc33_pci r4 vddq ae34 vcc33_pci r5 vddq ae36 vcc33_pci u8 vddq af15 vcca_fc ac13 vddq af26 vcca_spi4 ab13 vddq af28 vccr g10 vddq ag31 vccr g12 vddq ag34 vccr g20 vddq ag36 vccr g21 vddq ah11 vccr g23 vddq ah13 vccr g25 vddq ah15 vccr g29 vddq ah17 vccr g32 vddq ah20 vccr g33 vddq ah22 vccr g35 vddq ah24 vccr g37 vddq ah26 vccr g4 vddq ah28 vccr g7 vddq aj31 vccr g8 vddq aj34 vccra g19 vddq aj36 vccra g22 vddq ak8 vccra g30 vddq al10 vccra g34 vddq al12 vccra g5 vddq al14 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 13 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description 80 datasheet vddq al16 vddq al21 vddq al19 vddq al23 vddq aa26 vddq al25 vddq aa31 vddq al27 vddq ab28 vddq al29 vddq ab33 vddq al34 vddq ab35 vddq al36 vddq ac31 vddq an34 vddq ac34 vddq an36 vddq ac36 vddq ap11 vddq ad28 vddq ap13 vddq ap15 vddq at29 vddq ap17 vddq at31 vddq ap21 vddq at33 vddq ap23 vddq at35 vddq ap25 vddq at5 vddq ap27 vddq at7 vddq ap29 vddq at9 vddq ap31 vddq h34 vddq ap33 vddq m36 vddq ap5 vddq n31 vddq ap9 vddq p28 vddq ar2 vddq p34 vddq ar36 vddq p36 vddq ar4 vddq r31 vddq at1 vddq t28 vddq at11 vddq t34 vddq at13 vddq t36 vddq at15 vddq u31 vddq at17 vddq v28 vddq at19 vddq v34 vddq at21 vddq w31 vddq at23 vddq y28 vddq at25 vddq y34 vddq at27 vddq y36 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 14 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description datasheet 81 vddq h35 vss b30 vddq j31 vss b31 vddq k34 vss b32 vddq k36 vss b33 vddq l31 vss b34 vddq m34 vss b35 vrefhi ac11 vss b2 vrefhi al5 vss b5 vrefhi_clk h29 vss b6 vreflo ac12 vss b7 vreflo al6 vss b8 vreflo_clk h30 vss b9 vref_qdr0 at2 vss b10 vref_qdr0 au3 vss b11 vref_qdr1 at32 vss ab17 vref_qdr1 au33 vss ab19 vref_qdr2 at37 vss ab21 vref_qdr2 au36 vss ab23 vref_qdr3 h36 vss ab25 vref_qdr3 h37 vss ab26 vss b12 vss ab32 vss b14 vss ab37 vss b15 vss ac14 vss b16 vss ac16 vss b17 vss ac18 vss b19 vss ac20 vss b21 vss ac22 vss b22 vss ac24 vss b23 vss ac26 vss b24 vss ac27 vss b25 vss ac29 vss b26 vss ac3 vss b27 vss ac7 vss b28 vss ad12 vss b29 vss ad15 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 15 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description 82 datasheet vss b36 vss ad17 vss b3 vss ad19 vss b4 vss ad21 vss a37 vss ad23 vss aa12 vss ad25 vss aa14 vss ad26 vss aa16 vss ad27 vss aa18 vss ad32 vss aa20 vss ad34 vss aa22 vss ad37 vss aa24 vss ae1 vss aa29 vss ae16 vss aa34 vss ae18 vss aa5 vss ae20 vss aa9 vss ae22 vss ab1 vss ae26 vss ab15 vss ae29 vss ae5 vss ak34 vss ae9 vss ak37 vss af13 vss ak9 vss af14 vss al3 vss af16 vss am11 vss af17 vss am13 vss af20 vss am15 vss af25 vss am16 vss af32 vss am17 vss af34 vss am20 vss af37 vss am22 vss ag12 vss am24 vss ag13 vss am26 vss ag17 vss am28 vss ag22 vss am30 vss ag29 vss am32 vss ag7 vss am34 vss ah10 vss am37 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 16 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description datasheet 83 vss ah16 vss am5 vss ah3 vss am9 vss ah32 vss an2 vss ah34 vss ap10 vss ah37 vss ap12 vss ah5 vss ap14 vss aj1 vss ap16 vss aj10 vss ap18 vss aj12 vss ap20 vss aj14 vss ap22 vss aj15 vss ap24 vss aj16 vss ap26 vss aj18 vss ap28 vss aj19 vss ap30 vss aj21 vss ap32 vss aj23 vss ap34 vss aj25 vss ap37 vss aj27 vss ap6 vss aj29 vss ap8 vss ak32 vss ar1 vss ar3 vss d28 vss au1 vss d29 vss au10 vss d3 vss au12 vss d30 vss au14 vss d31 vss au16 vss d32 vss au2 vss d33 vss au22 vss d34 vss au24 vss d35 vss au26 vss d36 vss au28 vss d4 vss au30 vss d5 vss au32 vss d6 vss au34 vss d7 vss au37 vss d8 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 17 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description 84 datasheet vss au4 vss d9 vss au6 vss e1 vss au8 vss e13 vss c1 vss e14 vss c13 vss e18 vss c14 vss e2 vss c18 vss e20 vss c2 vss e22 vss c20 vss e27 vss c27 vss e34 vss c37 vss e37 vss d10 vss e9 vss d11 vss f10 vss d12 vss f11 vss d15 vss f12 vss d16 vss f13 vss d17 vss f15 vss d19 vss f16 vss d21 vss f17 vss d22 vss f19 vss d23 vss f21 vss d24 vss f22 vss d25 vss f23 vss f24 vss k32 vss f25 vss l11 vss f26 vss l19 vss f27 vss l23 vss f28 vss l34 vss f29 vss l35 vss f3 vss l37 vss f30 vss l5 vss f32 vss m1 vss f33 vss m16 vss f35 vss m19 vss f36 vss m32 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 18 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description datasheet 85 vss f4 vss n14 vss f5 vss n16 vss f7 vss n18 vss f8 vss n20 vss g13 vss n22 vss g14 vss n24 vss g16 vss n29 vss g18 vss n34 vss g2 vss n37 vss g27 vss p13 vss g31 vss p15 vss g6 vss p17 vss h10 vss p19 vss h14 vss p2 vss h17 vss p21 vss h18 vss p23 vss h23 vss p27 vss h31 vss p32 vss h4 vss p9 vss j30 vss r14 vss j34 vss r16 vss j37 vss r18 vss k17 vss r20 vss k19 vss r22 vss k2 vss r24 vss k30 vss r29 vss r3 vss v21 vss r34 vss v23 vss r37 vss v25 vss r6 vss v26 vss t13 vss v32 vss t15 vss v36 vss t17 vss w10 vss t19 vss w14 vss t21 vss w16 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 19 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description 86 datasheet vss t23 vss w18 vss t25 vss w20 vss t26 vss w22 vss t32 vss w24 vss u14 vss w26 vss u16 vss w29 vss u18 vss w34 vss u2 vss w4 vss u20 vss w8 vss u22 vss y13 vss u24 vss y15 vss u29 vss y17 vss u34 vss y19 vss u6 vss y2 vss u9 vss y21 vss v10 vss y23 vss v12 vss y25 vss v13 vss y26 vss v15 vss y32 vss v17 vss n25 vss v19 table 19. ixp2800/ixp2850 network processor alphabetical pin list (sheet 20 of 20) pin name fcbga location pin name fcbga location
intel ? ixp2800 and ixp2850 network processors signal description datasheet 87 3.3 pullup/pulldown and unused pin guidelines all unused inputs should be tied to their inactive state. typical pullup/pulld own resistor values are in the range of 1 ? 5k ohms. the following unused or floating lvds input pins should be terminated to vcc25, using a 400-ohm pullup resistor and to vss, using a 330-ohm pulldown resistor. ? spi4_rprot_h ? spi4_rprot_l ? spi4_rctl_h ? spi4_rctl_l ? spi4_rpar_h ? spi4_rpar_l ? fc_rxcpar_h ? fc_rxcpar_l ? fc_rxcsof_h ? fc_rxcsof_l ? fc_rxcdat_h(0) ? fc_rxcdat_h(1) ? fc_rxcdat_h(2) ? fc_rxcdat_h(3) ? fc_rxcdat_l(0) ? fc_rxcdat_l(1) ? fc_rxcdat_l(2) ? fc_rxcdat_l(3) ? fc_txcfc_h ? fc_txcfc_l ? fc_rxcclk_h ? fc_rxcclk_l ? fc_rxcsrb_h ? fc_rxcsrb_l alternatively, these pins can be tied directly to the 1.4 v (pullu p) or 1.0 v (pulldown) supplies without the need for termination resistors. in th is scenario, the 1.0 v / 1.4 v supplies must be capable of suppling the extra 7 ma of power per di fferential pin pair requ ired for the termination. all of the following test signals should be tied to logical 0 when not used: ? clk_stop ? clk_pll_byp
intel ? ixp2800 and ixp2850 network processors signal description 88 datasheet ? test_scan_en ? test_scan_mode ? test_diode_a ? test_diode_c ? spi4_preemp ? fc_preemp all of the following test signals should be tied to logical 1 when not used: ? test_scan_clk_a ? test_scan_clk_b
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 89 4.0 electrical specifications this chapter specifies the following electrical behavior of the network processor: ? absolute maximum ratings ? dc values and ac timing specifications for the following: ? pci i/o unit ? qdr ? rdram ? flow control bus ? spi-4 and csix ? slowport i/o buffer. ?gpio ?jtag ? serial port 4.1 absolute maximum ratings operating beyond the functional operating temperature range ( table 21 ) is not recommended and extended exposure beyond the functional operati ng temperature range may affect reliability. table 23 lists the functional operating voltage range. warning: under all operating conditions, the 3.3 v ? 1.35/ 1.3/1.2 v and 3.3 v ? 2.5 v supply voltage difference (vdelta) must not be exceeded; otherwise, permanent damage to the device may result. also, the core/pll supply voltage must never be less than 1.1 v (refer to table 20 ). table 20. absolute maximum ratings table parameter minimum maximum comment junction temp tj (commercial) ? 120 c junction temp tj (extended) ? 120 c storage temperature range -55 c 125 c supply voltage difference vdelta ? 2.7 v ? 3.3 v to 2.5 v rail difference. ? 3.3 v to 1.35/1.3/1.2 v rail difference. vcore (1.35/1.3 v) minimum operating voltage 1.1 v ? vcore (1.2 v) minimum operating voltage 1.1 v ?
intel ? ixp2800 and ixp2850 network processors electrical specifications 90 datasheet table 21. functional operating temperature range parameter minimum maximum comment commercial temperature operating range 0 c 70 c refer to the intel ? ixp2800 network processor thermal/mechanical design guideline application note . extended temperature operating range -40 c 85 c refer to the intel ? ixp2800 network processor thermal/mechanical design guideline application note . maximum junction temperature (extended) ? 120 c refer to the intel ? ixp2800 network processor thermal/mechanical design guideline application note . maximum junction temperature (commercial) ? 120 c refer to the intel ? ixp2800 network processor thermal/mechanical design guideline application note . table 22. typical and maximum power 1 1. the maximum power parameters represent the worst case pow er consumption as measured running the intel packet over sonet (pos) reference design processing minimum size packets (49 bytes) running at full oc-192 line rate. device 2 2. total power. typical maximum frequency ixp2800 - b n 3 3. b n refers to b0 and b1. 25.5 w 31.5 w 1.4 ghz ixp2800 - b n 18.5 w 23 w 1.0 ghz ixp2800 - b n 12.5 w 16 w 650 mhz ixp2850 - b n 27.5 w 34 w 1.4 ghz ixp2850 - b n 20.5 w 25 w 1.0 ghz ixp2850 - b n 14 w 17.5 w 650 mhz
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 91 table 23. functional operating voltage range ? 1.4/1.0 ghz interface supply name description voltage (v) tolerance (+/-%) notes 1,2,3,4,5 1. these supplies can be derived from core vcc, but should be filtered appropriately. 2. qdr references should be derived from vddq so that they track fluctuations in vddq. 3. during power-up, after nreset is de-asserted, the device will ex perience an increase in current consumption after the pll locks and the system clocks begin to operate at full speed. during this time a droop on the core power supply may occur due to this increase in current consumption. it is acceptable that the core power supply droop a maximum of 100 mv to a minimum of 1.2 v during this time. it is expected th at the device be idle during this time and that no instructions be executing until the power is within the 5% regulation specification. the behavior is undefined if instructions are executed while the power is not within the 5% regulation specification. 4. spi-4 reference should be derived from vcc25v so that they track fluctuations in vcc25v. 5. the tolerance on the pci supply is tighter than specified in the pci local bus specification, version 2.2* . core vcc vss core power supply core ground 1.3 v gnd 5% n/a 3 clock/pll vcc_pll vss vcc_clk pll power pll ground ref. clock power (also for gpio) 1.3 v gnd 2.50 v 5% n/a 5% 1 , 3 spi-4/csix/f low vcc25v vcca_fc vcca_spi4 vrefhi vreflo spi-4 supply (also for pci) dll power dll power spi-4/flow reference voltage spi-4/flow reference voltage 2.50 v 1.3 v 1.3 v 1.40 v 1.00 v 5% 5% 5% 5% 5% 1 1 4 4 gpio vcc33 gpio, jtag, sp power 3.30 v 5% pci vcc33_pci pci power supply 3.30 v 5% 5 qdr vddq pas0_vcca pas1_vcca pas2_vcca pas3_vcca vref_qdr0 vref_qdr1 vref_qdr2 vref_qdr3 qrd power supply dll power dll power dll power dll power qdr reference voltage qdr reference voltage qdr reference voltage qdr reference voltage 1.50 v 1.3 v 1.3 v 1.3 v 1.3 v 0.75 v 0.75 v 0.75 v 0.75 v 1.4 v to 1.6 v 5% 5% 5% 5% 0.7 v to 0.85 v 0.7 v to 0.85 v 0.7 v to 0.85 v 0.7 v to 0.85 v 1 1 1 1 2 2 2 2 rdr vccr vccra vccrio par0_padvrefa par0_padvrefb par1_padvrefa par1_padvrefb par2_padvrefa par2_padvrefb rdram core processor rdram clean power rdram i/o power rdram reference voltage rdram reference voltage rdram reference voltage rdram reference voltage rdram reference voltage rdram reference voltage 1.3 v 1.3 v 1.80 v 1.40 v 1.40 v 1.40 v 1.40 v 1.40 v 1.40 v 5% 5% 1.7 v to 1.9 v 1.2 v to 1.6 v 1.2 v to 1.6 v 1.2 v to 1.6 v 1.2 v to 1.6 v 1.2 v to 1.6 v 1.2 v to 1.6 v 1 fuse vcc_fuse fuse power supply 1.3 v 5%
intel ? ixp2800 and ixp2850 network processors electrical specifications 92 datasheet table 24. functional operating voltage range ? 650 mhz interface supply name description voltage (v) tolerance (+/-%) notes 1,2,3,4 1. these supplies can be derived from core vcc, but should be filtered appropriately. 2. qdr references should be derived from vddq so that they track fluctuations in vddq. 3. spi-4 reference should be derived from vcc25v so that they track fluctuations in vcc25v. 4. the tolerance on the pci supply is tighter than specified in the pci local bus specification, version 2.2* . core vcc vss core power supply core ground 1.2 v gnd 5% n/a clock/pll vcc_pll vss vcc_clk pll power pll ground ref. clock power (also for gpio) 1.2 v gnd 2.50 v 5% n/a 5% 1 spi-4/csix/f low vcc25v vcca_fc vcca_spi4 vrefhi vreflo spi-4 supply (also for pci) dll power dll power spi-4/flow reference voltage spi-4/flow reference voltage 2.50 v 1.2 v 1.2 v 1.40 v 1.00 v 5% 5% 5% 5% 5% 1 1 3 3 gpio vcc33 gpio, jtag, sp power 3.30 v 5% pci vcc33_pci pci power supply 3.30 v 5% 4 qdr vddq pas0_vcca pas1_vcca pas2_vcca pas3_vcca vref_qdr0 vref_qdr1 vref_qdr2 vref_qdr3 qrd power supply dll power dll power dll power dll power qdr reference voltage qdr reference voltage qdr reference voltage qdr reference voltage 1.50 v 1.2 v 1.2 v 1.2 v 1.2 v 0.75 v 0.75 v 0.75 v 0.75 v 1.4 v to 1.6 v 5% 5% 5% 5% 0.7 v to 0.85 v 0.7 v to 0.85 v 0.7 v to 0.85 v 0.7 v to 0.85 v 1 1 1 1 2 2 2 2 rdr vccr vccra vccrio par0_padvrefa par0_padvrefb par1_padvrefa par1_padvrefb par2_padvrefa par2_padvrefb rdram core processor rdram clean power rdram i/o power rdram reference voltage rdram reference voltage rdram reference voltage rdram reference voltage rdram reference voltage rdram reference voltage 1.2 v 1.2 v 1.80 v 1.40 v 1.40 v 1.40 v 1.40 v 1.40 v 1.40 v 5% 5% 1.7 v to 1.9 v 1.2 v to 1.6 v 1.2 v to 1.6 v 1.2 v to 1.6 v 1.2 v to 1.6 v 1.2 v to 1.6 v 1.2 v to 1.6 v 1 fuse vcc_fuse fuse power supply 1.2 v 5%
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 93 ? table 25. example power by supply ? 1.4 ghz type group names ixp2800 max power 1 1. power specified is in the total for all the supplies/references in each group. ixp2850 max power 1 1.3 v logic vcc vccr vccra vcc_fuse 25.5 w 28.0 w power 1.3 v pll/dll vcc_pll vcca_fc vcca_spi4 pas0_vcca pas1_vcca pas2_vcca pas3_vcca 1.0 w 1.0 w supplies 1.50 v vddq 2.0 w 2.0 w 1.80 v vccrio 0.5 w 0.5 w 2.5 v vcc_clk vcc25v 1.8 w 1.8 w 3.3 v vcc33 vcc33_pci 0.7 w 0.7 w 0.75 vref_qdr0 vref_qdr1 vref_qdr2 vref_qdr3 < 0.01 w < 0.01 w voltage references 1.0 v vreflo < 0.01 w < 0.01 w 1.4 v vrefhi par0_padvrefa par0_padvrefb par1_padvrefa par1_padvrefb par2_padvrefa par2_padvrefb < 0.01 w < 0.01 w
intel ? ixp2800 and ixp2850 network processors electrical specifications 94 datasheet table 26. example power by supply ? 1.0 ghz type group names ixp2800 max power 1 1. power specified is in the total for all the supplies/references in each group. ixp2850 max power 1 1.3 v logic vcc vccr vccra vcc_fuse 17.0 w 19.0 w power 1.3 v pll/dll vcc_pll vcca_fc vcca_spi4 pas0_vcca pas1_vcca pas2_vcca pas3_vcca 1.0 w 1.0 w supplies 1.50 v vddq 2.0 w 2.0 w 1.80 v vccrio 0.5 w 0.5 w 2.5 v vcc_clk vcc25v 1.8 w 1.8 w 3.3 v vcc33 vcc33_pci 0.7 w 0.7 w 0.75 v vref_qdr0 vref_qdr1 vref_qdr2 vref_qdr3 < 0.01 w < 0.01 w voltage references 1.0 v vreflo < 0.01 w < 0.01 w 1.4 v vrefhi par0_padvrefa par0_padvrefb par1_padvrefa par1_padvrefb par2_padvrefa par2_padvrefb < 0.01 w < 0.01 w
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 95 table 27. example power by supply ? 650 mhz type group names ixp2800 max power 1 1. power specified is in the total for all the supplies/references in each group. ixp2850 max power 1 1.2 v logic vcc vccr vccra vcc_fuse 10.4 w 11.8 w power 1.2 v pll/dll vcc_pll vcca_fc vcca_spi4 pas0_vcca pas1_vcca pas2_vcca pas3_vcca 1.0 w 1.0 w supplies 1.50 v vddq 1.9 w 1.9 w 1.80 v vccrio 0.4 w 0.4 w 2.5 v vcc_clk vcc25v 1.7 w 1.7 w 3.3 v vcc33 vcc33_pci 0.7 w 0.7 w 0.75 v vref_qdr0 vref_qdr1 vref_qdr2 vref_qdr3 < 0.01 w < 0.01 w voltage references 1.0 v vreflo < 0.01 w < 0.01 w 1.4 v vrefhi par0_padvrefa par0_padvrefb par1_padvrefa par1_padvrefb par2_padvrefa par2_padvrefb < 0.01 w < 0.01 w
intel ? ixp2800 and ixp2850 network processors electrical specifications 96 datasheet 4.2 supply voltage power-up sequence caution: the ixp2800/ixp2850 has a prescribed supply voltage bring-up sequence that must be followed or permanent damage to the device may result. 4.2.1 sequence for 1.4 / 1.0 ghz devices the sequence for the 1.4 / 1.0 ghz b-stepping devices is as follows: 1. the 2.5 v supply must come up before the 1.3 v supply. 2. the 1.3 v supply must come up after the 2.5 v supply and must not start to ramp until the 2.5 v supply has reached greater than 1 v. 3. the 3.3 v supply must come up only after the 2.5 v and 1.3 v supplies are up and stable. a. it is acceptable to ramp the 1.3 v and 3.3 v supplies together as long as the two supplies rise linearly together and do not deviate by mo re than 10% of the nominal ramp rate until both supplies reach their resp ective final voltage levels. it is expected that all supplies will be up and stable within the maximum power-up time requirement of 700 ms. additionally, the maximum time from when the 2.5 v supply is up and stable to when the 1.3 v supply begins to ramp should not exceed 200 ms. note: the 1.8 v and 1.5 v supplies can come up in any order before or after the 2.5 v, 1.3 v, and 3.3 v supplies. note: no 3.3 v devices should drive any of the ixp2800/ixp2850 pins until its 3.3 v supply is up and stable. 4.2.2 sequence for 650 mhz devices the sequence for the 650 mhz b-stepping devices is as follows: 1. the 2.5 v supply must come up before the 1.2 v supply. 2. the 1.2 v supply must come up after the 2.5 v supply and must not start to ramp until the 2.5 v supply has reached greater than 1 v. 3. the 3.3 v supply should begin to ramp after the 2.5 v and 1.2 v supplies are up and stable. a. it is acceptable to ramp the 1.2 v and 3.3 v supplies together as long as the two supplies rise linearly together and do not deviate by mo re than 10% of the nominal ramp rate until both supplies reach their resp ective final voltage levels. it is expected that all supplies will be up and stable within the maximum power-up time requirement of 700 ms. additionally, the maximum time from when the 2.5 v supply is up and stable to when the 1.2 v supply begins to ramp should not exceed 200 ms. note: the 1.8 v and 1.5 v supplies can come up in any order before or after the 2.5 v, 1.2 v, and 3.3 v supplies. note: no 3.3 v devices should drive any of the ixp2800/ixp2850 pins until its 3.3 v supply is up and stable.
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 97 4.3 lc filter network figure 10 shows an example of an lc f ilter design that can be used to derive the power for the analog and dll power supplies for the ixp2800/ixp2850. for l1, a 10-ohm ferrite bead with a dcr of less than 0.1 ohms should be used. for c1, a 10 microfarad capacitor should be used and each analog vcc pin should be de-coupled with a 0.1 microfarad and a 0.01 microfarad capacitor. 4.4 ac/dc specifications 4.4.1 clock timing specifications the ixp2800/ixp2850 has a centralized clock generato r that takes an external reference frequency and multiplies it to a higher base frequency clock, using a pll. the resulting clock frequency is then divided down by a set of programmable divisors to provide clocks to the sram, dram, and optionally, the media and switch fabric (msf) controllers. all of the dram controllers are clocked at the same rate, and therefore derive their clocks from a single divisor. each sram controller has a divisor, enabling it to be clocked individually. the intel xscale ? core and microengines derive their clocks from fixed-divide ratios. the msf derives its clock from either the intern al pll or an external source, such as a mac device. the selection is based on a the sp_ad[6] strap pi n. when the pin is high, the msf uses an internally-generated clock using the programmable divisor. when the pin is low, the msf uses an externally-received clock. refer to section 3.2.11, ?configuration pins? on page 41 for additional details. the pci controller also uses external clocks. an external oscillator (clk_ref_clk_h/l) generates the initial ixp2800/ixp2850 clock frequency. the clk_ref_clk range is between 75 to 125 mhz. the multiplier, used to generate the pll output frequency, is selected from strap b its sp_ad[5:0], and is in the range from 16 to 48. figure 10. lc filter network b0138-02 .01 f 0.1 f .01 f 0.1 f .01 f 0.1 f l1 = 10 1.35v 1.3v 1.2v c1 = 10 f
intel ? ixp2800 and ixp2850 network processors electrical specifications 98 datasheet note: only even multipliers are supported; refer to section 3.2.11, ?configuration pins? on page 41 for more information. the individual internal clocks are generated by dividing the highest frequency clock by various programmable integers (in the ra nge from 3 to 15) followed by another division by 2. note: the apb clock frequency cannot be configured to operate slower than the slowport clock (sp_clk) frequency; otherwise, the slowport i/o may be repeated indefinitely. the apb clock frequency is controlled via the cap clock_control register and the sp_clk frequency is controlled via the cap sp_ccr register. note: the dram_clk_ratio divisor value programmed in the cap clock_control register must always be greater than or equal to 6, to avoid data corruption. note: no external device (msf) can be configured to run faster than the internal command push-pull (cpp) bus frequency. the cpp frequency is always ? of the microengine frequency, which at 1.4 ghz is 700 mhz, at 1.0 ghz is 500 mhz, and at 650 mhz is 325 mhz. figure 11. ref_clk timing b3527-01 t pl clk_ref_clk_h vh vl overshoot undershoot rising edge ringback falling edge ringback clk_ref_clk_l threshold region crossing voltage crossing voltage ringback margin t ph t p t p t2 t5 t6 t ph t pl = t1 (clk_ref_clk (h,l) period) = clk_ref_clk(h,l) period stability (not shown) = t3 (clk_ref_clk(h,l) pulse high time) = t4 (clk_ref_clk(h,l) pulse low time) = clk_ref_clk(h,l) rise time through the threshold region = clk_ref_clk(h,l) fall time through the threshold region notes:
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 99 table 30 shows the frequencies that are available for dram, sram, and msf, based on various values of the pll output clock. table 28. ref_clk dc specifications symbol parameter minimum typical maximum unit notes 1 , 2 , 3 4 , 5 , 6 , 7 , 8 1. not a functional spec. reliability limit. 2. crossing voltage is defined as the absolute voltage where the rising edge of clk_ref_clk_h is equal to the falling edge of clk_ref_clk_l. guaranteed by design simulations. 3. as defined in ieee 1596.3. 4. guaranteed by design. 5. overshoot is defined as the absolute value of the maximum voltage allowed. 6. undershoot is defined as the absolute minimum voltage allowed. 7. ringback margin is defined as the absolute voltage difference between the maximum rising edge ringback and the maximum falling edge ringback. 8. threshold region is defined as a region entered at the crossi ng voltage in which the differential receiver switches. it inclu des input threshold hysteresis. vabsolute absolute voltage range ? 0.3 ? vcc25 + 0.3 v 1 vi input common mode voltage range 825 ? 1575 mv vcross crossing voltage 875 1200 1525 mv 2, 3, 4 vov overshoot n/a n/a vcc25 + 0.3 v 5 , 4 vus undershoot ? 0.3 n/a n/a v 6, 4 vrbm ringback margin 0.200 n/a n/a v 7, 4 vth threshold margin vcross ? 0.100 ? vcross + 0.100 v 8, 4 table 29. ref_clk ac specifications parameter minimum typical maximum unit notes 1,2 , 3 , 4 , 5 , 6 1. these specifications apply to clk_ref_clk. 2. guaranteed by design. 3. the period specified here is the average period. a given period may vary from this specification, as governed by the period stability specification. 4. rise/fall time is measured between the 20% and 80% points of the clock swing. 5. maximum combination of determinstic and random jitter components. 6. this parameter is not tested. it is guaranteed by design. low cycle-to-cycle input jitter (<16ps) can be guaranteed by design if all the following conditions are met: good board layout, good supply decoupling, <1? between resistor terminator and ixp28xx, and a high-quality oscillator (such as an epson ultra- low jitter saw oscillator). the use of translators is allowed, but not recommended because additional jitter will be introduced. if any of these conditions are not met, the cycle-to-cycle ji tter must be measured in the system to co nfirm that max jitter spec is met. reference clock input frequency 75 100 125 2 mhz t1: clk_ref_clk_(l/h) period 13.3 ? 8 ns 3 clk_ref_clk input duty cycle 40 50 60 % 2 t5: clk_ref_clk_(l/h) rise time ? ? 1 ns 2, 4 t6: clk_ref_clk_(l/h) fall time ? ? 1 ns 2, 4 period jitter peak-to-peak 50 2 ps jitter cycle-tocycle 16 ps 5, 6
intel ? ixp2800 and ixp2850 network processors electrical specifications 100 datasheet 4.4.2 maximum supported operating frequencies table 31 lists the maximum operating frequencie s for the associated network processor internal/external functional units . the maximum external interf ace operating frequencies are only available using the 1.4 ghz parts. table 30. clock rates examples input oscillator frequency (mhz) 100 pll output frequency (mhz) [pll multiplier] 1 2000 [20] 2200 [22] 2400 [24] 2600 [26] 2800 [28] 4000 [40] 4800 [48] microengine frequency 2 1000 1100 1200 1300 1400 2000 2400 intel xscale ? core & command/push/pull bus frequency 3 500 550 600 650 700 1000 1200 divide ratio for other units (except apb) 4 divisor 5 2 6 500 550 600 650 700 1000 1200 3 333 367 400 433 467 666 800 4 250 275 300 325 350 500 600 5 200 220 240 260 280 400 480 6 167 183 200 217 233 334 400 7 143 157 171 186 200 286 342 8 125 138 150 163 175 250 300 9 111 122 133 144 156 222 266 10 100 110 120 130 140 200 240 11 91 100 109 118 127 182 218 12 83 92 100 108 117 166 200 13 77 85 92 100 107 154 184 14 71 79 86 93 100 142 172 15 67 73 80 87 93 134 160 1. this multiplier is selected via sp_ad[5:0] strap pins. 2. this frequency is the pll output frequency divided by 2. 3. this frequency is the pll output frequency divided by 4. 4. the abp divisor specified in the clock_cont rol cap csr is scaled by an additional x4. 5. this divisor is selected via the clock_control cap csr. base frequency is the pll output frequency divided by 2. 6. this divide ratio is only used by test logic. in the normal functional mode, this ratio is reserved for push/pull clocks only . table 31. maximum supported operating frequencies device microengine frequency qdr frequency rdr 1 frequency 1. the minimum supported frequency for the rdr interface is 400 mhz. msf 2,3 frequency 2. derived from an external source. 3. the minimum supported frequency for the msf interface is 200 mhz. pci frequency rpixp2800bb 1.4 ghz 233 mhz 4 4. these frequencies cannot be achieved simultaneously with a 1.4 ghz microengine operating frequency. 533 mhz 4 500 mhz 66 mhz RPIXP2800BA 1.0 ghz 200 mhz 400 mhz 400 mhz 66 mhz rpixp2800bc 650 mhz 163 mhz 432 mhz 400 mhz 66 mhz rpixp2850bb 1.4 ghz 233 mhz 533 mhz 500 mhz 66 mhz rpixp2850ba 1.0 ghz 200 mhz 400 mhz 400 mhz 66 mhz rpixp2850bc 650 mhz 163 mhz 432 mhz 400 mhz 66 mhz
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 101 4.4.3 maximum clock frequencies the clock frequency for each interface is derived from an integer divide in the range of 3 to 15 of the microengine operating frequency. as such, a device running at 1.4 ghz cannot simultaneously achieve the maximum operating frequenc y for all of the external interfaces. table 32 lists examples of the maximum frequencies achievable, ba sed on the microengine clock frequency. 4.4.4 clock dc parameters the following clock-related signals use lvttl signaling levels as shown in table 33 . ? clk_phase_ref ? clk_stop ? clk_pll_byp ? clk_nreset ? clk_nreset_out table 32. example maximum clock frequencies 1 1. all values are in mhz. device ref_clk pll multiplier pll output microengine qdr rdr 2 2. actual internal frequency is the rdr frequency divided by 4. msf 3 3. if internally derived from the pll, the maxi mum frequency for an external source is listed in tab l e 3 1 . rpixp2800bc rpixp2850bc 81.25 16 1300 650 163 432/108 325 divisors 4 6 2 rpixp2800bb, rpixp2850bb 100 28 2800 1400 233 508/127 466 divisors 6 11 3 rpixp2800bb, rpixp2850bb 100 24 2400 1200 200 533/133 400 divisors 6 9 3 rpixp2800bb, rpixp2850bb 100 25 2500 1250 208 500/125 416 divisors 6 10 3 RPIXP2800BA, rpixp2850ba 100 20 2000 1000 200 400/100 333 divisors 5 10 3 table 33. clock buffer dc specifications (sheet 1 of 2) parameter conditions symbol minimum maximum unit notes 1 , 2 input high (logic 1) voltage vcc = 3.0 to 3.6 v vih 2.0 vdd + 0.3 v 1 input low (logic 0) voltage vcc = 3.0 to 3.6 v vil -0.3 0.8 v 1 input leakage current 0 v vin vdd ili -10.0 10.0 ua output leakage current outputs disabled, 0 v vin vdd ilo -10.0 10.0 ua
intel ? ixp2800 and ixp2850 network processors electrical specifications 102 datasheet 4.4.5 pci i/o unit this section specifies the following el ectrical behavior for the pci i/o unit. ? dc specifications ? ac timing specifications 4.4.5.1 pci dc specifications note: in table 34 , currents into the chip (chip sinking) are denoted as positive (+) current. currents from the chip (chip sourcing) are denoted as negative (-) current. input leakage currents include high-z output leakage for all bidirectional buffers with th ree-state outputs. the elec trical specifications are preliminary and subject to change. 4.4.5.2 pci overshoot/undershoot specifications the pci i/os are designed to be tolerant of overshoot and undershoot associated with normal i/o switching. however, excessive overshoot or undershoot of i/o signals can cause the device to latch up. table 35 specifies limits on i/o overshoot and undershoot that should never be exceeded. table 36 lists the maximum pci interface loading. output high voltage ioh = -4.0 ma voh 2.4 n/a v 1, 2 output low voltage iol = 4.0 ma vol n/a 0.4 v 1, 2 supply voltage vdd 3.1 3.5 v 1 1. all voltages referenced to vss (gnd). 2. the load used for voh and vol testing is shown in figure 22 . ac load current is higher than the shown dc values. table 33. clock buffer dc specifications (sheet 2 of 2) parameter conditions symbol minimum maximum unit notes 1 , 2 table 34. pci dc specifications symbol parameter condition minimum maximum v ih input high voltage 0.5 x vcc33 vcc33 + 0.5 v v il input low voltage ? 0.3 x vcc33 v oh output high voltage ioh = -500 ua 0.9 x vcc33 ? v ol output low voltage iol = 1500 ua ? 0.1 x vcc33 i i input leakage current 1 1. input leakage currents include high-impedance output leakage for all bidirectional buffers with three-state outputs. 0 vin vcc33 -10 ua 10 ua c in pin capacitance 5 pf 10 pf table 35. overshoot/undershoot specifications pin type undershoot overshoot maximum duration input ? 0.7 v 1 vcc33 +0.7 1 4 ns output ? 0.7 v 1 vcc33 +0.7 1 4 ns
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 103 4.4.5.3 pci ac specifications the ac specifications consist of input requiremen ts and output responses. the input requirements consist of setup and hold times, pulse widths, and high and low times. output responses are delays from clock to signal. the pci pins support the basic set of pci electrical specifications in the pci local bus specification, version 2.2* , which describes the pci i/o protocol and pin ac specifications. 4.4.5.4 pci clock signal ac parameter measurements 1. design requirement. guaranteed by design. table 36. maximum loading bus interface maximum number of loads trace length (inches) pci four loads at 66-mhz bus frequency eight loads at 33-mhz bus frequency 5 to 7 figure 12. pci clock signal ac parameter measurements table 37. 66 mhz pci clock signal ac parameters symbol parameter minimum maximum unit t cyc pci_clk cycle time 15 ? ns t high pci_clk high time 1 1. not tested. guaranteed by design. 6?ns tl ow pci_clk low time 1 6?ns pci_clk slew rate 1, 2 2. 0.2 vcc33 to 0.6 vcc33. 1.5 4 v/ns a9392-01 t cyc t f t r v t3 notes: v t1 = 0.5 v cc 33 v t2 = 0.4 v cc 33 v t2 = 0.3 v x 33 v t1 v t2 t high t low
intel ? ixp2800 and ixp2850 network processors electrical specifications 104 datasheet 4.4.5.5 pci bus signals timing table 38. 33 mhz pci clock signal ac parameters symbol parameter minimum maximum unit t cyc pci_clk cycle time 30 ? ns t high pci_clk high time 1 1. not tested. guaranteed by design. 11 ? ns t low pci_clk low time 1 11 ? ns pci_clk slew rate 1,2 2. 0.2 vcc33 to 0.6 vcc33. 14v/ns figure 13. pci bus signals table 39. 33 mhz pci signal timing symbol parameter minimum maximum unit t val clk to signal vali d delay, bused signals 1 1. bused signals are ad, cbe_l, par, perr_l, serr_l, frame_l, irdy_l, trdy_l, devsel_l, and stop_l. 211ns t val (point-to-point) clk to signal valid delay, point-to-point signals 2 2. point-to-point signals are req_l and gnt_l. 212ns t on float to active delay 3 3. not tested. guaranteed by design. 2? t off active to float delay 3 ?28ns t su input setup time to clk, bused signals 4 4. bused signals are ad, cbe_l, par, perr_l, serr_l, frame_l, irdy_l, trdy_l, devsel_l, and stop_l. 7?ns t su (point-to-point) input setup time to clk, point-to-point signals 5 5. point-to-point signals are req_l and gnt_l. 10 ? ns t h input signal hold time from clk 0 ? ns a9393-01 t val(max) t su t h t val(min) t on t off v test pci_clk outputs inputs note: v test = 0.4 v cc 33 for 3.3 volt pci signals
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 105 4.4.6 sram this section contains ac and dc parameters for the qdr. table 40. 66 mhz pci signal timing symbol parameter minimum maximum unit t val clk to signal valid delay, bused signals 1 1. bused signals are ad, cbe_l, par, perr_l, serr_l, frame_l, irdy_l, trdy_l, devsel_l, and stop_l. 16ns t val (point-to-point) clk to signal valid delay, point-to-point signals 2 2. point-to-point signals are req_l and gnt_l. 16ns t on float to active delay 3 3. not tested. guaranteed by design. 2? t off active to float delay 3 ?6ns t su input setup time to clk, bused signals 4 4. bused signals are ad, cbe_l, par, perr_l, serr_l, frame_l, irdy_l, trdy_l, devsel_l, and stop_l. 3?ns t su (point-to-point) input setup time to clk, point-to-point signals 5 5. point-to-point signals are req_l and gnt_l. 5?ns t h input signal hold time from clk 0 ? ns table 41. qdr dc specifications symbol parameter conditions minimum maximum unit notes 1 , 2 , 3 , 4 1. all voltages are referenced to vss (gnd). 2. overshoot: vih (ac) vdd + 0.7 v for t t3.0 ns. 3. not tested. design requirement validated by simulations. 4. hstl outputs meet jedec hstl class i standard. v ih input high voltage (logic 1) vref + 0.1 vddq + 0.3 v 1, 2 v il input low voltage (logic 0) -0.3 vref - 0.1 v 1, 2 v in clock input signal voltage -0.3 vddq + 0.3 v 1, 2, 3 i li input leakage current 0 v vin vddq -25 25 ua i lo output leakage current output(s) disabled, 0 v vin vddq (q) -25 25 ua v oh output high voltage |ioh| 0.1ma vddq - 0.2 vddq v 1, 4 v ol output low voltage iol 0.1ma vss 0.2 v 1, 4 v dd supply voltage 1.25 1.45 v 1 v ddq isolated output buffer supply 1.4 1.6 v 1 v ref reference voltage 0.7 0.8 v 1
intel ? ixp2800 and ixp2850 network processors electrical specifications 106 datasheet figure 14 shows the timing goals for the ixp2800/ixp2850 qdrii interface. all timing references are the rising edges of c and c# or k and k#, for receiver and tr ansmitter, respectively. note: the system designer must ensure that th e design implementation meets the sram k-clock-to-c-clock timing relationship, as speci fied in the sram datasheet. this may require additional trace routing on the base board to the c_0/1 clock, to en sure that it always lags the kclock. table 43 lists the qdr clock skew and figure 14 shows timing goals for the qdrii interface. table 42. qdr signal timing qdrii frequency 233 mhz 200 mhz 167 mhz 133 mhz min max min max min max min max input timing setup time 1 , 2 (ns) 1. not tested. guaranteed by simulations 2. the specified setup time is negative, whic h means that the data can arrive at the pi ns up to the specified time after the ris ing edge of the clock as shown in figure 14 . -0.70 -0.77 -0.97 -1.27 hold time (ns) 1 1.45 1.73 2.03 2.43 output timing output valid (ns) 1 -0.65 -0.9 -1.10 -1.37 output hold (ns) 1 0.65 0.9 1.10 1.37 k_0/1 to output skew at c4 bump 1 , 3 (ns) 3. the c4 bump is the connection point of the silicon die to th e package. this parameter specifies the skew between k0 and k1 clock and write data, address, and write/read port select out put signals, but does not include the mismatch introduced by the package substrate routing. -0.19 0.19 -0.20 0.20 -0.22 0.22 -0.23 0.23 k_0/1 to output skew at package ball 1 , 4 (ns) 4. this parameter specifies the skew between k0 and k1 clock and write data, address, and write/read port select output signals, including the mismatch introduced in the package substrate routing. -0.28 0.28 -0.29 0.29 -0.31 0.31 -0.32 0.32 table 43. qdr clock skew (sheet 1 of 2) description 1 , 2 166 mhz 200 mhz 233 mhz min max min max min max k rise to k# rise 3 2.78 ns 3.22 ns 2.30 ns 2.70 ns 1.81 ns 2.19 ns k# rise to k rise 3 2.78 ns 3.22 ns 2.30 ns 2.70 ns 1.81 ns 2.19 ns c rise to c# rise 3 2.78 ns 3.22 ns 2.30 ns 2.70 ns 1.81 ns 2.19 ns c# rise to c rise 3 2.78 ns 3.22 ns 2.30 ns 2.70 ns 1.81 ns 2.19 ns k_m rise to k_n rise 3 -0.18 ns 0.18 ns -0.15 ns 0.15 ns -0.14 ns 0.14 ns k_m# rise to k_n# rise 3 -0.18 ns 0.18 ns -0.15 ns 0.15 ns -0.14 ns 0.14 ns c_m rise to c_n rise 3 -0.18 ns 0.18 ns -0.15 ns 0.15 ns -0.14 ns 0.14 ns
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 107 c_m# rise to c_n# rise 3 -0.18 ns 0.18 ns -0.15 ns 0.15 ns -0.14 ns 0.14 ns k_m rise to c_m rise 3 -0.22 ns 0.22 ns -0.20 ns 0.20 ns -0.19 ns 0.19 ns k_m# rise to c_m# rise 3 -0.22 ns 0.22 ns -0.20 ns 0.20 ns -0.19 ns 0.19 ns 1. 2. specified at device package ball, which includes package substrate routing skew. 3. not tested. guaranteed by design simulations figure 14. qdr signal timing table 43. qdr clock skew (sheet 2 of 2) description 1 , 2 166 mhz 200 mhz 233 mhz min max min max min max m 01 , {} n 01 , {} mn , , a9624-01 cin# cin setup time hold time q k d output hold output valid receiver d0 d0
intel ? ixp2800 and ixp2850 network processors electrical specifications 108 datasheet 4.4.7 rdram table 45 lists the supported loading configurations, table 44 lists the rdram dc parameters, and table 46 lists the rdram ac parameters. table 44. rdram dc parameters symbol parameter minimum maximum unit vccr, vccra supply voltage 1.28 1.42 v vterm termination voltage 1.7 1.9 v vref reference voltage 1.2 1.6 v vcis,ctm 1, 2 1. vcis applies to both clock and clock . 2. guaranteed by design. clock input voltage swing on ctm pin 0.25 0.70 v vcis, cfm 1, 2 clock voltage swing on cfm pin 0.25 0.70 v vx 2 clock differential crossing-point voltage 1.30 1.80 v vcm 2 clock input common-mode voltage 1.40 1.70 v vdil 3 data input low voltage vref -0.5 vref -0.175 v vdih 2 data input high voltage vref +0.175 vref +0.5 v vdis 2 data input voltage swing 0.4 1.0 v adi 2 data input asymmetry about v ref -15% 15% vdis iol,test output current test condition @ vol = 0.9 v ? 30 ma cmd, sck 3 3. 28-ohm external termination with 0.9 v (thevenin equivalent). vol ?0.3 0.5*vccrio ? 0.25 v cmd, sck 3 voh 0.5*vccrio + 0.25 0.5*vccrio + 0.3 v pclkm, synclkn, sio 4 4. no termination. vol ? 0.3 0.3*vccrio v pclkm, synclkn, sio 4 voh 0.7*vccrio vccrio + 0.3 v sio vil ? 0.3 0.3*vccrio v sio vih 0.7*vccrio vccrio + 0.3 v table 45. rdram loading bus interface maximum number of loads trace length (inches) short channel: 400 and 533 mhz 4 devices per channel. 20 1 long channel: 400 mhz 2 rimms per channel ? a maximum of 32 devices in both rimms. 20 1 long channel: 533 mhz 1 rimm and 1 c-rimm per channel ? a maximum of 16 devices. 20 1
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 109 4.4.8 spi-4 and csix this section describes the para meters for the media and switch fabric (msf) interface. these parameters apply whether the bus is configured to carry spi-4 packets/cel ls or csix c-frames. 4.4.8.1 dc parameters table 47 lists applicable dc thresholds for lvttl, table 48 lists applicable driver dc thresholds for lvds, and table 49 lists applicable receiver dc thresholds for lvds. 1. for termination, the drams should be located as close as possible to the ixp2800 network processor.. table 46. rdram ac parameters symbol parameter minimum maximum unit tcycle ctm, cfm cycle time 1.875 2.50 ns tcycle, slow slow-mode ctm, cfm cycle time 5.00 ? ns tcr, tcf 1 , 2 1. measured from 20% ? 80% of input voltage swing. 2. guaranteed by design. ctm, cfm input rise and fall times 0.20 0.50 ns tch, tcl ctm 2 cfm high and low times 40% 60% tcycle ttr 2 ctm-to-cfm differential ? 0.26 ns tdr, tdf 2 data input rise and fall times 0.20 0.50 ns ts, th 2 , 3 3. for sck = 1 mhz. data-to-clock setup and hold times 800 mhz speed grade 3 1066 mhz speed grade 0.175 0.140 ? ns ns tqr - tqf 2 data output rise and fall time 3 0.18 0.40 ns tq 2 clock-to-data output time 800 mhz speed grade 3 1066 mhz speed grade -0.250 -0.180 0.250 0.180 ns ns tccinterval 2 iol calibration interval ? 100 ms tj, rc 2 rdram cmos clock jitter sck ?1.0ns ts, th, rc 2 sio to sck setup and hold times 1.0 ? ns tq, rc 2 sck to data out sck rise to cmd sck fall to sio 3 ?-10 -490 ns
intel ? ixp2800 and ixp2850 network processors electrical specifications 110 datasheet 4.4.8.2 ac parameters system-level reference points for sp ecified parameters are shown in figure 15 . corresponding reference points with respect to the clock edge are shown in figure 16 , figure 17 , and figure 18 . table 47. spi-4 lvttl dc thresholds symbol parameter min (v) max (v) v_oh output high voltage 2.4 3.6 v_ih input high voltage 2.0 3.6 v_il input low voltage ? 0.8 v_ol output low voltage ? 0.4 table 48. spi-4 lvds driver dc specifications symbol parameter min max voh output voltage high ? 1375 mv 1 1. output voltage valid when vrefhi = 1.4 v and vreflo = 1.0 v. the following equations determine the excursions when the voltage references and rzq are not held at nominal: ioh = 2 * ((vrefhi ? vreflo) / rzq) / 3 (valid when rload = rzq) iol = -2 * ((vrefhi ? vreflo) / rzq) / 3 (valid when rload = rzq) vol output voltage low 1025 mv 1 ? vod 2 2. guaranteed by design output differential voltage 150 mv 250 mv vos 2 output offset voltage 1150 mv 1250 mv 1 ro 2 output impedance, single ended 40 ohms 140 ohms table 49. spi-4 lvds receiver dc specifications symbol parameter min max vi input voltage range 825 mv 1575 mv vidth input differential threshold ? 100 mv + 100 mv vhyst 1 1. guaranteed by design. input differential hysteresis 25 mv ? ri 1 receiver differential input impedance 80 ohms 120 ohms
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 111 data path timing two sets of data path timing parameters are specifi ed to support different bit alignment schemes at the receiver. table 50 provides the corresponding parameters fo r the case of ?static alignment? in which the receiver latches data at a fixed point in ti me relative to clock (re quiring a more precisely specified sampling window). table 51 provides the corresponding parameters for th e case of ?dynamic alignment? in which the receiver has the capability of centering the data an d control bits relative to clock. from an ac timing perspective, a compliant interface only need s to meet the parameters at the data path for either static or dynamic alignment, but may also comply to both sets of parameters. a compliant driver must meet both timing sp ecifications to be interoperabl e with both types of receivers. figure 15. system level reference points a9322-01 source ab dc tdat / rdat[15:0] tctl / rctl tdclk / rdclk tstat / rstat[1:0] tsclk / rsclk sink figure 16. reference points for data path timing parameters b1406-01 (a) t dib t dia (a) t sampling g_max clk
intel ? ixp2800 and ixp2850 network processors electrical specifications 112 datasheet table 50. data path interfac e timing (static alignment) symbol parameter min max units fd tdclk / rdclk frequency 200 500 mhz tdclk / rdclk duty cycle 1 1. guaranteed by design. 45 55 % t_dia, t_dib 1 data invalid window with respect to clock edge (reference point a). ? 280 ps g_max 1 worst-case cumulative skew and jitter contribution (reference point b). ? 790 ps tsampling 1 data valid window with respect to clock edge. (reference point b) ? 1/(2?d) - g_max ps 20% - 80% rise and fall times (ui = ? fd) (reference point a) (reference point b) 100 ps 100 ps 0.30 ui 0.36 ui ui ui comments: 1. rise and fall times assume nominal 100-ohm termination and exclude reflections. 2. all timing parameters are measured relative to t he differential crossing point of the corresponding clock signal. 3. jitter parameters are peak-to-peak, measured above fd/1000 and below fd. 4. receiver sensitivity is assumed to be less than or equal to 100 mv. 5. assumes a 5 pf output load at reference point a, a 10 pf load at reference point b, and a 50-ohm transmission line in-between. 6. assumes up to a 20 ps skew between traces of a differential pair. table 51. data path interfac e timing (dynamic alignment) symbol parameter min max unit fd tdclk / rdclk frequency 200 500 mhz ? tdclk / rdclk jitter (at reference point a) 1 1. guaranteed by design. ? 0.10 ui ? tdat / rdat / tctl / rctl jitter (at reference point a) 1 ?0.24ui ? 20% - 80% rise and fall times 1 (ui = ? fd) (reference point a) (reference point b) 100 ps 100 ps 0.30 ui 0.36 ui ui ui comments: 1. rise and fall times assume nominal 100-ohm termination and exclude reflections. 2. all timing parameters are measured relative to t he differential crossing point of the corresponding clock signal. 3. jitter parameters are peak-to-peak, measured above fd/1000 and below fd. 4. receiver sensitivity is assumed to be less than or equal to 100 mv. 5. assumes a 5 pf output load at reference point a, a 10 pf load at reference point b, and a 50-ohm transmission line in-between. 6. assumes up to a 20 ps skew between traces of a differential pair.
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 113 table 52. transmitter and receiver ac timing parasitics fifo status channel the following section describes ac timing parameters for a fifo status channel implemented using lvttl i/o. as noted in table 53 , the maximum clock frequency of the lvttl fifo status channel must not exceed ? of the se lected data path clock rate. fo r an optional lvds fifo status channel configuration, implementers should refer to the lvds data path ac timing parameters specified in table 50 , table 51 , and table 52 . parameter min max units transmitter channel-to-channel skew 1 1. guaranteed by design. n/a 100 ps differential pair skew 1 n/a 50 ps tclk jitter 1 n/a 100 ps tclk_ref jitter 1 n/a 50 ps tclk duty cycle when sourced from internal pll 1 45 55 % tclk duty cycle when sourced from tclk_ref 1, 2 2. when tclk_ref is selected as the tclk source, the tclk_r ef duty cycle must be held to within 47.5% to 52.5% to main- tain the 45% to 55% output duty cycle; otherwise, the tclk duty cycle will be equal to the source tclk_ref duty cycle +/- 2.5%. 45 55 % txcclk duty cycle when sourced from internal pll 1 45 55 % txcclk duty cycle when sourced from tclk_ref/rclk 1, 3 3. when tclk_ref or rclk is selected as the txcclk source, the tclk_ref/rclk duty cycle must be held to within 47.5% to 52.5% to maintain the 45% to 55% output duty cycle; ot herwise, the txcclk duty cycle will be equal to the source tclk_ref/rclk duty cycle +/- 2.5%. 45 55 % receiver receiver data valid window 1, 4 4. this parameter specifies the receiver setup/hold requirement. th is is equal to three sample periods, and the sample period is the bit time/8. the dll in the receive path generates 16 unique sample clocks per cycle or 8 sample clocks per bit time. the receive data valid window must be at least 3 sample clocks wide. for example, at 350 mhz this is ((((1/350)/2))/8)*3 or 536 ps. 3*(bit time/8) 5 5. the bit time is the 1/cycle time of the interface divided by 2 for a double data rate bus. for example, at 350 mhz, the bit t ime is ((1/350/2) or 1.428 ns. n/a ps receiver data valid window 1, 6 6. valid for interface running at 350 mhz. 536 n/a ps receiver data valid window 1, 7 7. valid for interface running at 400 mhz. 469 n/a ps receiver data valid window 1, 8 8. valid for interface running at 500 mhz. 375 n/a ps
intel ? ixp2800 and ixp2850 network processors electrical specifications 114 datasheet figure 17. spi4-2 receive fifo status bus timing diagram b3053-01 rsclk rstat[1:0] rstat[1:0] td1 td2 table 53. spi4-2 receive fifo status bus timing parameters parameter symbol min max units rsclk frequency fs ? fd / 4 mhz rsclk falling edge to rstat[1:0] valid (active edge flipped to falling) 1 1. guaranteed by design. td1 0.5 4.0 ns rsclk rising edge to rstat[1:0] valid (default operation) 1 td2 0.5 4.0 ns figure 18. spi4-2 transmit fifo status bus timing diagram b3054-01 tsclk tstat[1:0] tstat[1:0] th1 tsu1 tsu2 th2
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 115 4.4.9 flow control bus this section lists the lvds parameters for the flow control bus. table 55 lists the driver dc specifications, table 56 lists the receiver dc specifications, and table 57 lists the clock specifications. the flow control bus ac timing para meters are the same as those specified for the spi-4 lvds data path; implementers should refer to table 50 , table 51 , and table 52 for ac timing details. table 54. spi4-2 transmit fifo status bus timing parameters parameter symbol min max units tstat[1:0] setup to tsclk rising edge (default operation) 1 1. guaranteed by design. tsu1 2.0 ? ns tstat[1:0] hold from tsclk rising edge (default operation) 1 th1 0.5 ? ns tstat[1:0] setup to tsclk falling edge (when active edge flipped to falling) 1 tsu2 2.0 ? ns tstat[1:0] hold from tsclk falling edge (when active edge flipped to falling) 1 th2 0.5 ? ns table 55. flow control bus lv ds driver dc specifications symbol parameter min max voh output voltage high ? 1375 mv vol output voltage low 1025 mv ? vod 1 1. guaranteed by design. output differential voltage 150 mv 250 mv vos 1 output offset voltage 1150 mv 1250 mv ro 1 output impedance, single-ended 40 ohms 140 ohms table 56. flow control bus lv ds receiver dc specifications symbol parameter min max vi input voltage range 825 mv 1575 mv vidth input differential threshold ? 100 mv + 100 mv vhyst 1 1. guaranteed by design. input differential hysteresis 25 mv ? ri 1 receiver differential input impedance 80 ohms 120 ohms
intel ? ixp2800 and ixp2850 network processors electrical specifications 116 datasheet 4.4.10 slowport i/o buffer this section lists the ac and dc parameters for the slowport. table 57. flow control bus clock specifications symbol parameter min max fd rx/txcclk 200 mhz 500 mhz rx/txcclk duty cycle 1 45% 55% 1. guaranteed by design. table 58. slowport i/o buffer dc specifications parameter conditions symbol minimum maximum unit notes 1 , 2 1. all voltages are referenced to vss (gnd). 2. the load used for voh and vol testing is shown in figure 19 . ac load current is higher than the dc values shown. input high (logic 1) voltage vcc = 3.0 to 3.6 v vih 2.0 vdd + 0.3 v 1 input low (logic 0) voltage vcc = 3.0 to 3.6 v vil -0.3 0.8 v 1 input leakage current 0 v vin vdd ili -10.0 10.0 ua output leakage current outputs disabled, 0 v vin vdd ilo -10.0 10.0 ua output high voltage ioh = -4.0 ma voh 2.4 ? v 1, 2 output low voltage iol = 4.0 ma vol 0.4 v 1, 2 supply voltage vdd 3.1 3.5 v 1
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 117 4.4.11 slowport timing 4.4.11.1 prom device timing information the following figures and tables provide timing information for the slowport. figure 19. transient equivalent testing load circuit for slowport i/o buffer a9332-01 351 5 pf q 317 3.3 v figure 20. single write tran sfer for self-timing device b0096-02 sp_ale_l sp_wr_l sp_rd_l sp_ack_l 02468101214161820 sp_clk a[1:0] 9:2 17: 10 25: 18 sp_cs_l [1:0] sp_a[1:0] sp_ad[7:0] d[7:0] t co 9:2 17: 10 25: 18 t co t co t co t co t su t h
intel ? ixp2800 and ixp2850 network processors electrical specifications 118 datasheet table 59. slowport write ac parameters 1 1. these timing parameters are specified for a 1.4 ghz core frequency and from the rising edge of sp_clk. guaranteed by functional test. external signals tco l max 2 /min (ns) 2. the default output timing is controlled by the txe register. refer to the intel ? ixp2400 and ixp2800 programmer?s reference manual for further details. by default, this register is set to a value of 0x1. for each increment to this register, a pclk period delay is added to both the maximum and minimum specified valu es. for example, for a pclk frequency of 700 mhz, a period delay is ~ 1.4 ns; using a txe register value of 0x5, the maxi mum and minimum delay values would be calculated as follows: max = 9.0 + (5- 1) * 1.4 = 14.6 ns. min = 1.5 + (5 - 1) * 1.4 = 7.1 ns. note : this delay should not exceed the cycle time of sp_clk. th 3 (ns) min 3. the sampling of the sp_ack_l signal is c ontrolled by the rxe register. refer to the intel ? ixp2400 and ixp2800 program- mer?s reference manual for further details. by default, this register is set to a value of 0x1. for each increment to this register, a pclk period delay is added to the setup and is subtracted fr om the hold specified values. for example, for a pclk frequen- cy of 700 mhz, a period delay is ~ 1.4 ns; using an rxe regist er value of 0x5, the setup and hold delay values would be cal- culated as follows: setup = 12.2 + (5-1) * 1.4 = 17.8 ns. hold = 1.0 - (5-1) * 1.4 = - 4.6 ns. note : this delay should not exceed the cycle time of sp_clk. tsu 3 (ns) min tpw (ns) loading (pf) sp_ale 9.0/1.5 50 sp_cs[0] 9.0/1.5 50 sp_cs[1] 9.0/1.5 50 sp_wr 9.0/1.5 50 sp_ack 1 12.2 sp_ad[1:0] 9.0/1.5 50 sp_ad[7:0] output to external device 9.0/1.5 figure 21. read transaction for self-timing device b2866-02 sp_ale_l sp_wr_l sp_rd_l sp_a[1:0] 02468101214161820 sp_clk 9:2 17: 10 24: 18 sp_cs_l [1:0] sp_ad[7:0] sp_ack_l t doz t co 9:2 d[7:0] d[7:0] 17: 10 24: 18 t su t h t dzo t co t co t h t h t co t co t h t co t su
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 119 4.4.12 gpio the gpio can be used with appropriate software in i 2 c applications. refer to philips semiconductors* i 2 c bus specification for the dc and ac characteristics. table 61 shows the dc characteristics for a fast mode i 2 c bus device. it can also be used for test purposes. table 60. slowport read ac parameters 1 external signals tco 2 l max/min (ns) th 3 (ns) min tsu (ns) min tpw (ns) toz/zo max/min (ns) loading (pf) sp_ale 9.0/1.5 50 sp_cs[0] 9.0/1.5 50 sp_cs[1] 9.0/1.5 50 sp_rd 9.0/1.5 50 sp_ack 1.0 12.2 sp_ad[1:0] 9.0/1.5 50 sp_ad[7:0] output to external device 9.0/1.5 12.2/1.0 sp_ad[7:0] input from external device 1.0 12.2 1. these timing parameters are specified for a 1.4 ghz core frequency and from the rising edge of sp_clk. guaranteed by functional tests. 2. the default output timing is controlled by the txe register; refer to the intel ? ixp2400 and ixp2800 programmer?s reference manual for further details. by default, this register is set to a valu e of 0x1. for each increment to this register, a pclk period delay is added to both the maximum and minimum specified valu es. for example, for a pclk frequency of 700 mhz, a period delay is ~ 1.4 ns; using a txe register value of 0x5, the ma ximum and minimum delay values would be calculated as follows: max = 9.0 + (5- 1) * 1.4 = 14.6 ns. min = 1.5 + (5 - 1) * 1.4 = 7.1 ns. note : this delay should not exce ed the cycle time of sp_clk. 3. the sampling of the sp_ack_l and sp_ad signals is controlled by the rxe register. refer to the intel ? ixp2400 and ixp2800 programmer?s reference manual for further details. by default, this register is set to a value of 0x1. for each incre- ment to this register, a pclk period delay is added to the setu p and is subtracted from the hold specified values. for exam- ple, for a pclk frequency of 700 mhz, a period delay is ~ 1. 4 ns; using an rxe register value of 0x5, the setup and hold delay values would be calculated as follows: setup = 12.2 + (5-1) * 1.4 = 17.8 ns. hold = 1.0 - (5-1) * 1.4 = - 4.6 ns. note : this delay should not exce ed the cycle time of sp_clk. table 61. gpio i/o buffer dc specifications parameter conditions symbol minimum maximum unit notes 1 , 2 input high (logic 1) voltage vih 2.0 vdd + 0.3 v 1 input low (logic 0) voltage vil -0.3 0.8 v 1 input leakage current 0 v vin vdd ili -10.0 10.0 ua output leakage current outputs disabled, 0 v vin vdd ilo -10.0 10.0 ua output high voltage ioh = -4.0 ma voh 2.4 - v 1, 2 output low voltage iol = 4.0 ma vol - 0.4 v 1, 2 supply voltage vdd 3.1 3.5 v 1
intel ? ixp2800 and ixp2850 network processors electrical specifications 120 datasheet 4.4.13 jtag 4.4.13.1 jtag dc electrical characteristics 1. all voltages referenced to vss (gnd). 2. the load used for voh and vol testing is shown in figure 22 . ac load current is higher than the dc values shown. figure 22. transient equivalent test ing load circuit for gpio i/o buffer table 62. jtag dc specifications symbol parameter conditions minimum maximum unit notes 1 , 2 1. all voltages referenced to vss (gnd). 2. the load used for voh and vol testing is shown in figure 23 . ac load current is higher than the dc values shown. vih input high (logic 1) voltage 2.0 vdd + 0.3 v 1 vil input low (logic 0) voltage -0.3 0.8 v ili input leakage current 0 v = vin = vdd -10.0 + 10.0 ua ilo output leakage current output(s) disabled, 0 v = vin = vdd -10.0 10.0 ua voh output high voltage ioh = -4.0 ma 2.4 v 1, 2 vol output low voltage iol = 8.0 ma 0.4 v 1, 2 vdd supply voltage 3.1 3.5 v 1 a9332-01 351 5 pf q 317 3.3 v
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 121 4.4.13.2 jtag ac characteristics figure 23. vih, vol load for testing a9332-01 351 5 pf q 317 3.3 v figure 24. boundary scan general timing a9333-01 tbscl tbsls tbsoh tbsod tck tms, tdi tdo data in data out tbsch tbsss tbslh tbssh tbsdh tbsdd
intel ? ixp2800 and ixp2850 network processors electrical specifications 122 datasheet figure 25. boundary scan three-state timing a9334-01 tbscl tbsoe tck tdo tbsch tbsoz tbsde data out tbsdz figure 26. boundary scan reset timing a9335-01 tbsr ntrst tms tbsrh tbsrs
intel ? ixp2800 and ixp2850 network processors electrical specifications datasheet 123 4.4.14 reset timing table 64 shows the reset timing specifications for clk_nreset. the basic reset timing sequence is shown in figure 27 . table 63. jtag ac specifications symbol parameter minimum typical maximum unit notes 1, 2, 3, 4, 5, 6, 7, 8, 9 tbscl tck low period 50 ? ? ns 1 tbsch tck high period 50 ? ? ns 1 tbsis tdi, tms setup to [tcr] 10 ? ? ns tbsih tdi, tms hold from [tcr] 10 ? ? ns tbsoh tdo hold time 5 ? ? ns 2 tbsod tcf to tdo valid ? ? 40 ns 2 tbsss i/o signal setup to [tcr] 5 ? ? ns 1,3 tbssh i/o signal hold from [tcr] 20 ? ? ns 1, 3 tbsdh data output hold time 5 ? ? ns 1, 4 tbsdd tcf to data output valid ? ? 40 ns 1 tbsoe tdo enable time 5 ? ? ns 1, 2, 5 tbsoz tdo disable time ? ? 40 ns 1, 2, 6 tbsde data output enable time 5 ? ? ns 1, 4, 7 tbsdz data output disable time ? ? 40 ns 1, 4, 8 tbsr reset period 30 ? ? ns 1 tbsrs tms setup to [trr] 10 ? ? ns 9 tberh tms hold from [trr] 10 ? ? ns 9 1. aaa guaranteed by design. 2. assumes a 25 pf load on tdo. output timing derates at 0.072 ns/pf of extra load applied. 3. for correct data latching, the i/o signals (from the core and the pads) must be set up and held with respect to the rising ed ge of tck in the capture-dr state of the sample/preload and extest instructions. 4. assumes that the data outputs are loaded with the ac test loads. 5. tdo enable time applies when the tap controller enters the shift-dr or shift-ir states. 6. tdo disable time applies when the tap contro ller leaves the shift-dr or shift-ir states 7. data output enable time applies when the boundary scan logic is used to enable the output drivers. 8. data output disable time applies when the boundary scan logic is used to disable the output drivers. 9. tck may be stopped indefinitely in either the low or high phase. table 64. reset timing specification symbol parameter 1 1. guaranteed by functional testing. minimum maximum unit t rst clk_nreset, must be asserted prior to vdd being stable. 1?ms t ss configuration strap pins 2 setup to nreset 5 reference clock cycles (ref_clk) 3 t hs configuration strap pins 2 hold from nreset 5 reference clock cycles (ref_clk) 3
intel ? ixp2800 and ixp2850 network processors electrical specifications 124 datasheet when the system is powered up, th e bypass clock is sent to all of the units as the chip begins to power up. it will be used to allow a gradual power-up and to begin clocking state elements to remove possible circuit contention. when the pll gets locked after clk_nreset is de-asserted, it will start generating ?divide-by-16? clocks for all of the units. a reset from the clk_nreset register is also removed at the same time. the reset sequence shown above is the same in th e case when reset happen s through the pci_rst# signal and cfg_rst_dir is asserted. 4.4.15 serial port the serial port consists of txd and rxd, which are asynchronous relative to any device outside of the network processor. the serial port io buffer dc specifications ar e the same as the gpio io dc buffer specifications. 2. this parameter is applicable to all of the configuration pins listed in section 3.2.11 . 3. ref_clk can be in the range of 75 - 125 mhz, as specified in table 29 ref_clk ac specifications . figure 27. reset timing b2668-02 configuration strap pins clk_ nreset ref _clk vdd t ss t rst ref_clk and vdd stable reset# de-assertion t hs
intel ? ixp2800 and ixp2850 network processors mechanical sp ecifications datasheet 125 5.0 mechanical specifications 5.1 package marking the ixp2800 network processor package marking is shown in figure 28 , and the ixp2850 network processor package marking is shown in figure 29 . product name stepping qdf number marketing part number version rpixp2800aa a0 q424 mm# 848953 1.0 ghz rpixp2800ab a0 q425 mm# 848954 1.4 ghz rpixp2800aa a1 q480 mm# 851637 1.0 ghz rpixp2800ab a1 q481 mm# 851649 1.4 ghz rpixp2800aa a2 q572 mm# 855314 1.0 ghz rpixp2800ab a2 q573 mm# 855311 1.4 ghz RPIXP2800BA b0 q668 mm# 857259 1.0 ghz rpixp2800bb b0 q669 mm# 857266 1.4 ghz RPIXP2800BA b1 q808 mm# 861093 1.0 ghz rpixp2800bb b1 q809 mm# 861099 1.4 ghz rpixp2800bc b1 q853 mm# 862906 650 mhz RPIXP2800BA b1 mm# 862117 1 1.0 ghz rpixp2800bb b1 mm# 855650 1 1.4 ghz rpixp2800bc b1 mm# 862907 1 650 mhz rpixp2850aa a0 q454 mm# 850268 1.0 ghz rpixp2850ab a0 q455 mm# 850269 1.4 ghz rpixp2850aa a1 q482 mm# 851648 1.0 ghz rpixp2850ab a1 q483 mm# 851646 1.4 ghz rpixp2850aa a2 q574 mm# 855312 1.0 ghz rpixp2850ab a2 q575 mm# 855313 1.4 ghz rpixp2850ba b0 q670 mm# 858140 1.0 ghz rpixp2850bb b0 q671 mm# 858141 1.4 ghz rpixp2850ba b1 q810 mm# 861102 1.0 ghz rpixp2850bb b1 q811 mm# 861132 1.4 ghz rpixp2850bc b1 q854 mm# 862908 650 mhz rpixp2850ba b1 mm# 862113 1 1.0 ghz rpixp2850bb b1 mm# 862114 1 1.4 ghz rpixp2850bc b1 mm# 862910 1 650 mhz 1. production-qualified devices are not marked with a qdf number.
intel ? ixp2800 and ixp2850 network processors mechanical specifications 126 datasheet figure 28. ixp2800 network processor package marking figure 29. ixp2850 network processor package marking b0475-01 level 1 name intel legal country of origin 2d matrix rpixp2800xx intel xxxx philippines m c (encoded assembly lot traceability mark) b0565-01 level 1 name intel legal country of origin 2d matrix rpixp2850xx intel xxxx philippines m c (encoded assembly lot traceability mark)
intel ? ixp2800 and ixp2850 network processors mechanical sp ecifications datasheet 127 5.2 package dimensions the network processor package dimensions are shown in figure 30 , figure 31 , and figure 32 and detailed in table 65 . figure 30. ixp2800/ixp2850 network processor package ball grid array a9208-03 s1 pin 1 corner ? b s2 e e au at ar ap an am al ak aj ah ag af ae ad ac ab aa y w v u t r p n m l k j h g f e d c b a 1 2 3 4 5 6 7 8 9 10111213141516171819202122232425262728293031323334353637 bottom (pin side) view
intel ? ixp2800 and ixp2850 network processors mechanical specifications 128 datasheet figure 31. ixp2800/ixp2850 network processor package top view a9207-02 top view e f1 d f2 figure 32. ixp2800/ixp2850 network processor package side view a9209-02 side view a3 seating plane a a1 c
intel ? ixp2800 and ixp2850 network processors mechanical sp ecifications datasheet 129 table 65. ixp2800/ixp2850 networ k processor package dimensions symbol minimum maximum a 3.891 4.565 a1 0.40 0.60 a3 2.266 2.49 b0.61 c 1.225 1.475 d 37.45 37.55 e 37.45 37.55 f1 33.4 33.6 f2 33.4 33.6 e1.00 s1 0.750 s2 0.750 notes: all dimensions are in millimeters (mm).
intel ? ixp2800 and ixp2850 network processors mechanical specifications 130 datasheet

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